21264/EV68A Hardware Reference Manual
Initialization and Configuration 7–19

Phase-Lock Loop (PLL) FunctionalDescription

7.11 Phase-Lock Loop (PLL) Functional Description
The PLL multipliesthe clock frequency of a differential input reference clock and
aligns the phase of its output to that differential input clock. Thus, the 21264/EV68A
can communicatesynchronously on clock boundaries with clock periods that are
defined bythe system.

7.11.1 DifferentialReference Clocks

A skew-controlled,ac-coupled differential clock is provided to the PLL by way of
ClkIn_x.ClkIn_xareinput signals to a differential amplifier. The frequency of
ClkIn_xcanrange from 80 MHz to 200 MHz. ClkIn_xcan be sour ced by a variety of
componentsthat include PECL fanout parts or system PLLs. ClkIn_xare also the pri-
mary clock sourcefor the 21264/EV68A when in PLL bypass mode.

7.11.2 PLLOutput Clocks

The followingsections summarize the PLL output clocks.
7.11.2.1 GCLK
The PLL providesa n outputclock, GCLK, with a frequency that can range from 400
MHz to 1.25 GHz under full-speedconditions. GCLK is the nominal onchip clock that
is distributedto the entire 21264/EV68A chip.
7.11.2.2 Differential 21264/EV68A Clocks
The EV6Clk_xoutputpads provide an external test point to measure the PLL phase
alignment.They do not provide a clock source. EV6Clk_xare square-w ave signals
that driverail-to-rail continually from 0 to VDD.
7.11.2.3 Nominal Operating Frequency
Undernormal operating conditions, the frequency of the PLL output clock, GCLK, is a
simplef unctionof theYdiv divider value.
DOWN2 Triggeredby duration counter reaching 8205 cycles,the PLL ramps GCLK frequency
downbythefirstdividerratio(X
divand Zdiv equal 2 and 4, respectively). This has the
effectof halving the GCLK frequency. The duration counter is set to 4108 cycles.
DOWN3 Triggeredby duration counter reaching 4108c ycles, the PLL ramps frequency down by
thesecond divider ratio (Xdiv and Zdivequal 16 and 32, respectively). This has the
effectof reducing the frequency by a factor of 16 (of the original frequency). The inter-
nalcounter is set to 264 cycles.
WAIT_INTERRUPT Triggeredby duration counter reaching 264 cycles,the 21264/EV68A waits for either an
unmaskedclock interrupt or unmasked device interrupt from system. Theinterrupts are
wired to the interrupt req uest and enable internal reg isters. When an enabled interru pt
occurs,the PLL ramps back to full frequency. Subsequentto that, the built-in self-init
(BiSI)initializes arrayed structures. The SROM is not reloaded; instead,t he 21264/
EV68A begins fetching code fromthe SYSTEM.
Table 7–11 21264/EV6 8ARe setS tate Machine StateD escriptions (Continued)
StateName Description