Compaq EV68A specifications Pllvdd

21264/EV68A Signal Names and Functions

Table 3–2 21264/EV68A Signal Descriptions (Continued)

Signal	Type	Count	Description
FrameClk_H	I_DA_CLK	2	A skew-controlled differential 50% duty cycle copy of the sys-
FrameClk_L			tem clock. It is used by the 21264/EV68A as a reference, or
			framing, clock.
IRQ_H[5:0]	I_DA	6	These six interrupt signal lines may be asserted by the system.
			The response of the 21264/EV68A is determined by the system
			software.
MiscVref	I_DC_REF	1	Voltage reference for the miscellaneous pins
			(see Table 3–3).
PllBypass_H	I_DA	1	When asserted, this signal will cause the two input clocks
			(ClkIn_x) to be applied to the 21264/EV68A internal circuits,
			instead of the 21264/EV68A global clock (GCLK).
PLL_VDD	2.5 V	1	2.5-V dedicated power supply for the 21264/EV68A PLL.
Reset_L	I_DA	1	System reset. This signal protects the 21264/EV68A from
			damage during initial power-up. It must be asserted until
			DCOK_H is asserted. After that, it is deasserted and the
			21264/EV68A begins its reset sequence.
SromClk_H	O_OD_TP	1	Serial ROM clock. Supplies the clock that causes the SROM to
			advance to the next bit. The cycle time for this clock is 256
			times the cycle time of the GCLK (internal 21264/EV68A
			clock).
SromData_H	I_DA	1	Serial ROM data. Input data line from the SROM.
SromOE_L	O_OD_TP	1	Serial ROM enable. Supplies the output enable to the SROM.
SysAddIn_L[14:0]	I_DA	15	Time-multiplexed command/address/ID/Ack from system to
			the 21264/EV68A.
SysAddInClk_L	I_DA	1	Single-ended forwarded clock from system for
			SysAddIn_L[14:0] and SysFillValid_L.
SysAddOut_L[14:0]	O_OD	15	Time-multiplexed command/address/ID/mask from the 21264/
			EV68A to the system bus.
SysAddOutClk_L	O_OD	1	Single-ended forwarded clock output for
			SysAddOut_L[14:0].
SysCheck_L[7:0]	B_DA_OD	8	Quadword ECC check bits for SysData_L[63:0].
SysData_L[63:0]	B_DA_OD	64	Data bus for memory and I/O data.
SysDataInClk_H[7:0]	I_DA	8	Single-ended system-generated clocks for clock forwarded
			input system data.
SysDataInValid_L	I_DA	1	When asserted, marks a valid data cycle for data transfers to
			the 21264/EV68A.
SysDataOutClk_L[7:0]	O_OD	8	Single-ended 21264/EV68A-generated clocks for clock for-
			warded output system data.
SysDataOutValid_L	I_DA	1	When asserted, marks a valid data cycle for data transfers from
			the 21264/EV68A.
SysFillValid_L	I_DA	1	When asserted, this bit indicates validation for the cache fill
			delivered in the previous system SysDc command.

21264/EV68A Hardware Reference Manual Hardware Interface 3–5