Compaq EV68A 5.2.17 Icache Flush Register IC_FLUSH, 5.2.18 Icache Flush ASM Register IC_FLUSH_ASM, 5.2.19 Clear Virtual-to-PhysicalMap Register CLR_MAP, 5.2.20 Sleep Mode Register SLEEP, 5.2.21 Process Context Register PCTX

21264/EV68A Hardware Reference Manual Internal Processor Registers 5–21
Ibox IPRs
5.2.17 Icache Flush Register – IC_FLUSH
The Icachef lushregister (IC_FLUSH) is a pseudo register. Writing to this register
invalidatesall Icache blocks. The cache is flushed when the next HW_RET/STALL
instructionis retired. See Section D.20 for more information.
5.2.18 Icache Flush ASM Register – IC_FLUSH_ASM
The Icache flush ASM register (IC_FLUSH_ASM)is a pseudo register.Writing to this
registerinvalidates all Icache blocks with their ASM bit clear.
5.2.19 Clear Virtual-to-PhysicalMap Register – CLR_MAP
The clear virtual-to-physicalmap register (CLR_MAP) is a pseudo register that, when
written,results in the clearing of the current map of virtualto physical registers. This
registermust only be written after there are no register-borne dependencies present and
there areno unretired instructions. See an example in the PALcoderestrictions.
5.2.20 Sleep Mode Register – SLEEP
The sleep mode register(SLEEP) is a pseudo register that, when written, results in the
PLL speed beingr educedand the chip entering a low-power mode. This register must
onlybe wr ittenafter a sequence of code has been run which saves all necessary state to
DRAM,flushes the caches, and unmasks certain interrupts so the chip can be woken up.
See Section 7.3 for details.
5.2.21 Process Context Register – PCTX
The processcontext register (PCTX) contains information associated with the context
of a process.Any combination of the bit fields within this register may be writtenwith
a singleHW _MTPR instruction.When bits [7:6] of the IPR index field of a
HW_MTPR instructioncontain the value 012, this register is selected. Bits [4:0]of the
IPR index indicatewhich bit fields are to be written. Usage of PCTX in performance
monitoringis described in Section 6.10.
Table5–13 lists the correspondence between IPR index bits and register fields.
A HW_MFPR from this register returnsthe values in all of its component bit fields.
Figure 5–24 shows theprocess context register.
Table 5–13 IPR Index Bits and Register Fields
IPRIndex Bit RegisterField
0ASN
1 ASTER
2ASTRR
3PPCE
4FPE