Compaq EV68A specifications Fast Data Mode

System Port

If both the sender and the receiver are sampling at the same rate, these three principles are sufficient to safely make point-to-point transfers using clock forwarding. However, it is often desirable for systems to align clock-forwarded transactions on a slower SYSCLK that is the basis of all non-processor system transactions.

The 21264/EV68A supports three ratios for SYSCLK to INT_FWD_CLK: one-to-one (1-1), two-to-one (2-1), and four-to-one (4-1). Using one of these ratios, the 21264/EV68A starts transactions on SYSCLK boundaries. This ratio is programmed into the 21264/EV68A using the Cbox CSR SYS_FRAME_LD_VECTOR[4:0]. This ratio is independent of the frequency of FrameClk_H.

For data movement, the 21264/EV68A reacts to SysDc commands when they are resolved into the 21264/EV68A’s clock domain. This occurs when the 21264/EV68A’s INT_FWD_CLK unloads the SysDc command from the clock forwarding queue. This moment is determined by the amount of delay programmed into the clock forwarding silo (by way of Cbox CSR SYS_RCV_MUX_CNT_PRESET[1:0]). Thus, all the tim- ing relationships are relative to this unload point in time, which will be referred to as the point the command is perceived by 21264/EV68A.

4.7.8.2 Fast Data Mode

The 21264/EV68A is the default driver of the bidirectional SysData bus1. As the 21264/EV68A is processing WrVictim, ProbeResponse (only the hit case), and IOWB commands to the system, accompanying data is made available at the clock-forwarded bus.

Because there is a bandwidth difference between address (4 cycles) and data (8 cycles) transfers, the 21264/EV68A tries to fully use fast data mode by delaying the next SysAddOut write command until a fast data mode slot is available on the SysDataOut bus.

SysDc commands (cache fill or explicit write commands) that collide with the fast data on the SysData bus have higher priority, and so may interrupt the successful completion of the fast transfer. Systems are responsible for detecting and replaying all interrupted fast transfers. There are no gaps in a fast transfer and no data wrapping (the first cycle contains QW0, addressed by PA[5:3] = 000).

The system must release victim buffers, and probe buffers and IOWB entries by send- ing a SysDc command with the appropriate RVB/RPB bit for both successful fast data transfers and for transfers that have been replayed. Fast data transfers have two parts:

1.SysAddOut command with the probe response, WrVictim, or Wr(I/O)

2.Data

The command precedes data by at least one SYSCLK period. Table 4–25shows the number of SYSCLK cycles between SysAddOut and SysData for all system clock ratios (clock forwarded bit times) and system framing clock multiples.

1The SysData bus contains SysData_L[63:0] and SysCheck_L[7:0].

21264/EV68A Hardware Reference Manual Cache and External Interfaces 4–31