Compaq EV68A specifications Floating-Point Control Register Fields, 36Internal Architecture

Floating-Point Control Register

Figure 2–11 Floating-Point Control Register

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47

SUM

INED

UNFD

UNDZ

DYN

IOV

INE

UNF

OVF

DZE

INV

OVFD

DZED

INVD

DNZ

The floating-point control register fields are described in Table 2–14.

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LK99-0050A

Table 2–14 Floating-Point Control Register Fields

Name	Extent	Type	Description
SUM	[63]	RW	Summary bit. Records bit-wise OR of FPCR exception bits.The summary bit is
			not directly modified by writes to bit 63 of the FPCR, but is indirectly modified
			by changes to FPCR bits 57–52.
INED	[62]	RW	Inexact Disable. If this bit is set and a floating-point instruction that enables
			trapping on inexact results generates an inexact value, the result is placed in the
			destination register and the trap is suppressed.
UNFD	[61]	RW	Underflow Disable. The 21264/EV68A hardware cannot generate IEEE com-
			pliant denormal results. UNFD is used in conjunction with UNDZ as follows:
				UNFD	UNDZ	Result
			0		X	Underflow trap.
			1		0	Trap to supply a possible denormal result.
			1		1	Underflow trap suppressed. Destination is written
						with a true zero (+0.0).
UNDZ	[60]	RW	Underflow to zero. When UNDZ is set together with UNFD, underflow traps
			are disabled and the 21264/EV68A places a true zero in the destination register.
			See UNFD, above.

2–36Internal Architecture 21264/EV68A Hardware Reference Manual