21264/EV68A Hardware Reference Manual
Internal Processor Registers 5–17
Ibox IPRs
ST_WAIT_64K [20] RW,0 ThestWait table is used to reduce load/storeorder traps.
When set, the stWait table is cleared after 6 4K cycles. When
clear, the stWait table is cleared after 16K cyc les. See Sec-
tion2.11.
PCT1_EN [19] RW,0 Enableperformance counter #1. Ifthis bit is one, the perfor-
mancecounter will count if either the system (SPCE) or pro-
cess (PPCE) performance c ounter enable is asserted.
PCT0_EN [18] RW,0 Enableperformance counter #0. Ifthis bit is one, the perfor-
mancecounter will count if EITHER the system (SPCE) or
process(PPCE) performance counter enable is set.
SINGLE_ISSUE_H [17] RW,0 When set, this bit forces instructionsto issue only from the
bottom-mostentries of the IQ and FQ.
VA_FORM_32 [16] RW,0 This bit controls address formatting on a read of the
IVA_FORMregister.
VA_48 [15] RW,0 Thisbit controls the format applied to effective virtual
addressesby the IVA_FORM register and the Ibox virtual
addresssign extension checkers. When VA_48is clear, 43-
bitvirtual address format is used, and when VA_48is set,
48-bitvirtual address format is used. The effect of this biton
theIVA_FORM register isidentical to the effect of
VA_CTL[VA_48]o n the VA_FORM register. See Sectio n
5.1.5.
WhenVA_48 is set, the sign extension checkersgenerate an
ACVif va[63:0] ≠SEXT(va[47:0]). When VA_48 is clear,
thesign extension checkers generate an ACV if va[63:0] ≠
SEXT(va[42:0]).
Thisbit also affects DTB_DOUBLE traps. If set, the DTB
doublemiss traps vector to the DTB_DOUBLE_4 entry
point.
DTB_DOUBLEPALcode flow selection is not affected by
VA_CTL[VA_48].
SL_RCV [14] RO See Section11.2.
SL_XMIT [13] WO Whenset, drives a valueon SromClk_H. See Section 11.2.
HWE [12] RW,0 Ifset, allow PALRES intructions to be executedin kernel
mode. Note that modification of the ITB while in kernel
mode/nativemode may cause UNPREDICTABLE behavior.
BP_MODE[1:0] [11:10] RW,0 BranchPrediction Mode Selection.
BP_MODE[1],if set, forces all branches to be predicted to
fallthrough. If clear, the dynamic branch predictor is chosen.
BP_MODE[0].If set, the dynamic branch predictor chooses
localhistory prediction. Ifclear, the dynamicbranch predic-
torchooses local or global prediction based on the state of
thechooser.
SBE[1:0] [9:8] RW,0 StreamBuffer Enable.
Thevalue in this bit field specifies the numberof Istream
bufferprefetches (besides the demand-fill) that are launched
afteran Icache miss. Ifthe value is zero, only demand
requestsare launched.
Table 5–11 Ibox Control Register Fields Descripti on(Co ntinued)
Name Extent Type Description