Compaq EV68A specifications Xiv

4–34	Rules for System Control of Cache Status Update Order	4–42
4–35	Range of Maximum Bcache Clock Ratios	4–43
4–36	Bcache Port Pins	4–43
4–37	BC_CPU_CLK_DELAY[1:0] Values	4–45
4–38	BC_CLK_DELAY[1:0] Values	4–45
4–39	Program Values to Set the Cache Clock Period (Single-Data)	4–46
4–40	Program Values to Set the Cache Clock Period (Dual-Data Rate)	4–46
4–41	Data-Sample/Drive Cbox CSRs	4–47
4–42	Programming the Bcache to Support Each Size of the Bcache	4–51
4–43	Programming the Bcache Control Pins	4–51
4–44	Control Pin Assertion for RAM_TYPE A	4–51
4–45	Control Pin Assertion for RAM_TYPE B	4–52
4–46	Control Pin Assertion for RAM_TYPE C	4–52
4–47	Control Pin Assertion for RAM_TYPE D	4–52
5–1	Internal Processor Registers	5–1
5–2	Cycle Counter Control Register Fields Description	5–4
5–3	Virtual Address Control Register Fields Description	5–5
5–4	ProfileMe PC Fields Description	5–8
5–5	IER_CM Register Fields Description	5–10
5–6	Software Interrupt Request Register Fields Description	5–11
5–7	Interrupt Summary Register Fields Description	5–12
5–8	Hardware Interrupt Clear Register Fields Description	5–13
5–9	Exception Summary Register Fields Description	5–14
5–10	PAL Base Register Fields Description	5–15
5–11	Ibox Control Register Fields Description	5–16
5–12	Ibox Status Register Fields Description	5–19
5–13	IPR Index Bits and Register Fields	5–21
5–14	Process Context Register Fields Description	5–22
5–15	Performance Counter Control Register Fields Description	5–23
5–16	Performance Counter Control Register Input Select Fields	5–25
5–17	DTB Alternate Processor Mode Register Fields Description	5–26
5–18	Memory Management Status Register Fields Description	5–28
5–19	Mbox Control Register Fields Description	5–30
5–20	Dcache Control Register Fields Description	5–31
5–21	Dcache Status Register Fields Description	5–32
5–22	Cbox Data Register Fields Description	5–33
5–23	Cbox Shift Register Fields Description	5–33
5–24	Cbox WRITE_ONCE Chain Order	5–34
5–25	Cbox WRITE_MANY Chain Order	5–39
5–26	Cbox Read IPR Fields Description	5–41
6–1	Required PALcode Function Codes	6–3
6–2	Opcodes Reserved for PALcode	6–3
6–3	HW_LD Instruction Fields Descriptions	6–4
6–4	HW_ST Instruction Fields Descriptions	6–5
6–5	HW_RET Instruction Fields Descriptions	6–6
6–6	HW_MFPR and HW_MTPR Instructions Fields Descriptions	6–7
6–7	Paired Instruction Fetch Order	6–9
6–8	PALcode Exception Entry Locations	6–13
6–9	IPRs Used for Performance Counter Support	6–18
6–10	Aggregate Mode Returned IPR Contents	6–19
6–11	Aggregate Mode Performance Counter IPR Input Select Fields	6–20
6–12	CMOV Decomposed	6–21
6–13	ProfileMe Mode Returned IPR Contents	6–22
6–14	ProfileMe Mode PCTR_CTL Input Select Fields	6–24
7–1	21264/EV68A Reset State Machine Major Operations	7–1
7–2	Signal Pin Reset State	7–3
7–3	Pin Signal Names and Initialization State	7–5
7–4	Power-Up Flow Signals and Their Constraints	7–7
7–5	Effect on IPRs After Fault Reset	7–8

xiv 21264/EV68A Hardware Reference Manual