Compaq EV68A specifications Hardware Interface, Cache and External Interfaces

2.3.1	Instruction Group Definitions	2–17
2.3.2	Ebox Slotting	2–18
2.3.3	Instruction Latencies	2–20
2.4	Instruction Retire Rules	2–21
2.4.1	Floating-Point Divide/Square Root Early Retire	2–22
2.5	Retire of Operate Instructions into R31/F31	2–22
2.6	Load Instructions to R31 and F31	2–23
2.6.1	Normal Prefetch: LDBU, LDF, LDG, LDL, LDT, LDWU, HW_LDL Instructions	2–23
2.6.2	Prefetch with Modify Intent: LDS Instruction	2–23
2.6.3	Prefetch, Evict Next: LDQ and HW_LDQ Instructions	2–24
2.7	Special Cases of Alpha Instruction Execution	2–24
2.7.1	Load Hit Speculation	2–24
2.7.2	Floating-Point Store Instructions	2–26
2.7.3	CMOV Instruction	2–26
2.8	Memory and I/O Address Space Instructions	2–27
2.8.1	Memory Address Space Load Instructions	2–27
2.8.2	I/O Address Space Load Instructions	2–27
2.8.3	Memory Address Space Store Instructions	2–28
2.8.4	I/O Address Space Store Instructions	2–29
2.9	MAF Memory Address Space Merging Rules	2–30
2.10	Instruction Ordering	2–30
2.11	Replay Traps	2–31
2.11.1	Mbox Order Traps	2–31
2.11.1.1	Load-Load Order Trap	2–31
2.11.1.2	Store-Load Order Trap	2–31
2.11.2	Other Mbox Replay Traps	2–32
2.12	I/O Write Buffer and the WMB Instruction	2–32
2.12.1	Memory Barrier (MB/WMB/TB Fill Flow)	2–32
2.12.1.1	MB Instruction Processing	2–33
2.12.1.2	WMB Instruction Processing	2–33
2.12.1.3	TB Fill Flow	2–34
2.13	Performance Measurement Support—Performance Counters	2–35
2.14	Floating-Point Control Register	2–35
2.15	AMASK and IMPLVER Instruction Values	2–37
2.15.1	AMASK	2–38
2.15.2	IMPLVER	2–38
2.16	Design Examples	2–38

3 Hardware Interface

3.1	21264/EV68A Microprocessor Logic Symbol	3–1
3.2	21264/EV68A Signal Names and Functions	3–3
3.3	Pin Assignments	3–8
3.4	Mechanical Specifications	3–17
3.5	21264/EV68A Packaging	3–18

4 Cache and External Interfaces

4.1	Introduction to the External Interfaces	4–1
4.1.1	System Interface	4–3
4.1.1.1	Commands and Addresses	4–4
4.1.2	Second-Level Cache (Bcache) Interface	4–4
4.2	Physical Address Considerations	4–4
4.3	Bcache Structure	4–7
4.3.1	Bcache Interface Signals	4–7
4.3.2	System Duplicate Tag Stores	4–7

iv 21264/EV68A Hardware Reference Manual