Compaq EV68A specifications Performance Counter Control Register Pctrctl

Ibox IPRs

Table 5–14 Process Context Register Fields Description (Continued)

Name	Extent	Type	Description
FPE	[2]	RW,1	Floating-point enable—if clear, floating-point instructions
			generate FEN exceptions. This bit is set by hardware on
			reset.
PPCE	[1]	RW	Process performance counting enable.
			Enables performance counting for an individual process
			with counters PCTR0 or PCTR1, which are enabled by set-
			ting PCT0_EN or PCT1_EN, respectively.
			Performance counting for the entire system can be enabled
			by setting I_CTL[SPCE]. See Section 5.2.15 for more infor-
			mation.
			See Section 6.10 for information about performance count-
			ing.
Reserved	[0]	—	—

5.2.22 Performance Counter Control Register – PCTR_CTL

The performance counter control register (PCTR_CTL) is a read-write register that controls the function of the performance counters for either aggregate counting or Pro- fileMe sampling counting.

Usage of PCTR_CTL in performance monitoring is described in Section 6.10.

Figure 5–25shows the performance counter control register.

Figure 5–25 Performance Counter Control Register

63 48 47 28 27 26 25 6 5 4 3 2 1 0

SEXT(PCTR0_CTL[47])

PCTR0[19:0]

PM_STALLED

PM_KILLED_BM

PCTR1[19:0]

SL0

SL1[1:0]

VAL

TAK

LK99-0034A

Table 5–15describes the performance counter control register fields.

Table 5–15 Performance Counter Control Register Fields Description

Name	Extent	Type	Description
SEXT(PCTR0_CTL[47])	[63:48]	RO	When read, this field is sign extended from PCTR_CTL[47]. Writes
			to this field are ignored.

21264/EV68A Hardware Reference Manual Internal Processor Registers 5–23