Compaq EV68A Restriction 25 Hwmtpr Itbia After Reset, 14PALcode Restrictions and Guidelines

Restriction 24: HW_RET/STALL After HW_MTPR IC_FLUSH, IC_FLUSH_ASM,

xxx

HW_ST/C -> R0

Bxx R0, try_again

STQ ; Force next ST/C to fail if no preceding LDxL

HW_RET

D.20 Restriction 24: HW_RET/STALL After HW_MTPR IC_FLUSH, IC_FLUSH_ASM, CLEAR_MAP

There must be a HW_RET/STALL after a HW_MTPR IC_FLUSH, IC_FLUSH_ASM, or CLEAR_MAP. The Icache flush associated with these instructions will not occur until the HW_RET/STALL occurs and all outstanding Istream fetches have been completed.

Also, there must be a guarantee that the HW_MTPR IC_FLUSH or HW_MTPR

IC_FLUSH_ASM will not be retired simultaneously with the HW_RET/STALL. This can be ensured by inserting a conditional branch between the two (BNE R31, 0 cannot be mispredicted in PALmode), or by ensuring at least 10 instructions between the MTPR instruction and the HW_RET/STALL containing at least one instruction in each quad aligned group with a valid destination. Finally, the HW_RET/STALL that is used for CLEAR_MAP cannot trigger a cache flush. That is, if both a CLEAR_MAP and IC_FLUSH are desired, there must be two HW_RET/STALLs, one following each HW_MTPR.

D.21 Restriction 25: HW_MTPR ITB_IA After Reset

An HW_MTPR ITB_IA is required in the reset PALcode to initialize the ITB. It is also required that PALcode not be exited, even via a mispredicted path until this HW_MTPR ITB_IA has been retired. PALmode can change temporarily after fetching a HW_RET, regardless of the STALL qualifier, down a mispredicted path leading to use of the ITB before it is actually initialized.

Unexpected instruction fetch and execution can occur following misprediction of any memory format control instruction (JMP, JSR, RET, JSR_CO, or HW_JMP, HW_JSR, HW_RET, HW_JSR_CO regardless of the STALL qualifier), or after any mispredicted conditional branch instruction. If the unexpected instruction flow contains a HW_RET instruction, PALmode may be exited prematurely.

One way to ensure that PALmode is not exited is to place the HW_MTPR ITB_IA at least 80 instructions before any possible HW_RET instruction can be encountered via any fetch path. Since memory format control instructions can mispredict to any cache location, they should also be avoided within these 80 instructions.

D.22 Guideline 26: Conditional Branches in PALcode

To avoid pollution of the branch predictors and improve overall branch prediction accu- racy, conditional branch instructions in PALcode will be predicted to not be taken. The only exception to this rule are conditional branches within the first cache fetch (up to four instructions) of all PALcode flows except CALL_PAL flows. Conditional branches should be avoided in this window.

D–14PALcode Restrictions and Guidelines 21264/EV68A Hardware Reference Manual