Compaq EV68A specifications Replay Traps, Mbox Order Traps

Replay Traps

The 21264/EV68A maintains the default I/O instruction ordering as shown in Table 2– 11 (assume address X and address Y are different).

Table 2–11 I/O Reference Ordering

First Instruction in Pair Second Instruction in Pair Reference Order

Load I/O to address X Load I/O to address X Store I/O to address X Store I/O to address X Load I/O to address X Load I/O to address X Store I/O to address X Store I/O to address X

Load I/O to address X	Maintained
Load I/O to address Y	Maintained
Store I/O to address X	Maintained
Store I/O to address Y	Maintained
Store I/O to address X	Maintained
Store I/O to address Y	Not maintained
Load I/O to address X	Maintained
Load I/O to address Y	Not maintained

2.11 Replay Traps

There are some situations in which a load or store instruction cannot be executed due to a condition that occurs after that instruction issues from the IQ or FQ. The instruction is aborted (along with all newer instructions) and restarted from the fetch stage of the pipeline. This mechanism is called a replay trap.

2.11.1 Mbox Order Traps

Load and store instructions may be issued from the IQ in a different order than they were fetched from the Icache, while the architecture dictates that Dstream memory transactions to the same physical bytes must be completed in order. Usually, the Mbox manages the memory reference stream by itself to achieve architecturally correct behavior, but the two cases in which the Mbox uses replay traps to manage the memory stream are load-loadand store-loadorder traps.

2.11.1.1 Load-Load Order Trap

The Mbox ensures that load instructions that read the same physical byte(s) ultimately issue in correct order by using the load-loadorder trap. The Mbox compares the address of each load instruction, as it is issued, to the address of all load instructions in the load queue. If the Mbox finds a newer load instruction in the load queue, it invokes a load-loadorder trap on the newer instruction. This is a replay trap that aborts the tar- get of the trap and all newer instructions from the machine and refetches instructions starting at the target of the trap.

2.11.1.2 Store-Load Order Trap

The Mbox ensures that a load instruction ultimately issues after an older store instruc- tion that writes some portion of its memory operand by using the store-loadorder trap. The Mbox compares the address of each store instruction, as it is issued, to the address of all load instructions in the load queue. If the Mbox finds a newer load instruction in the load queue, it invokes a store-loadorder trap on the load instruction. This is a replay trap. It functions like the load-loadorder trap.

21264/EV68A Hardware Reference Manual Internal Architecture 2–31