Compaq EV68A specifications PALshadow Registers, PALcode Emulation of the Fpcr

PALshadow Registers

6.5.6 Correct Ordering of Explicit Readers Followed by Implicit Writers

Certain IPRs that are updated as a result of faulting memory operations require PAL- code assistance to maintain ordering against newer instructions. Consider the following code sequence:

HW_MFPR IPR_MM_STAT

LDQ rx,(ry)

It is typically the case that these instructions would issue in-order:

•The MFPR is data-ready and both instructions use a lower subcluster. However, the HW_MFPRs (and HW_MTPRs) respond to certain resource-busy indications and do not issue when the MBOX informs the IBOX that a certain set of resources (store bubbles) are busy.

•The LDs respond to a different set of resource-busy indications (load-bubbles) and could issue around the HW_MFPR in the presence of the former. PALcode assis- tance is required to enforce the issue order.

One totally reliable method is to insert an MB (memory barrier) instruction before the first load that occurs after the HW_MFPR MM_STAT. Another method would be to force a register dependency between the HW_MFPR and the LD.

6.6 PALshadow Registers

The 21264/EV68A contains eight extra virtual integer registers, called shadow regis- ters, which are available to PALcode for use as scratch space and storage for com- monly used values. These registers are made available under the control of the SDE[1] field of the I_CTL IPR. These shadow registers overlay R4 through R7 and R20 through R23, when the CPU is in PALmode and SDE[1] is set.

PALcode generally runs with shadow mode enabled. Any PALcode that supports CALL_PAL instructions must run in that mode because the hardware writes a PALshadow register with the return address of CALL_PAL instructions.

PALcode may occasionally be required to toggle shadow mode to obtain access to the overlayed registers. See the PALcode restriction, Updating I_CTL[SDE], in Section D.32.

6.7 PALcode Emulation of the FPCR

The FPCR register contains status and control bits. They are accessed by way of the MT_FPCR and MF_FPCR instructions. The register is physically implemented like an explicitly written IPR. It may be written with a value from the floating-point register file by way of the MT_FPCR instruction. Architecturally-compliant FPCR behavior requires PALcode assistance. The FPCR register must operate as listed here:

1.Correct operation of the status bits, which must be set when a floating-point instruction encounters an exceptional condition, independent of whether a trap for the condition is enabled.

2.Correct values must be returned when the FPCR is read by way of a MF_FPCR instruction.

21264/EV68A Hardware Reference Manual Privileged Architecture Library Code 6–11