Compaq EV68A specifications Bcache Data Single-Bit Correctable ECC Error, Dcache Fill from Bcache

Bcache Data Single-Bit Correctable ECC Error

•C_ADDR contains bits [42:6] of the Bcache fill address of the block that contains the error.

•C_SYNDROME_0[7:0] and C_SYNDROME_1[7:0] contain the syndrome of quadword 0 and 1, respectively, of the octaword subblock that contains the error.

•A machine check (MCHK) is posted and taken immediately. The PALcode machine check handler performs a scrubbing operation as described in Section D.36 to ensure that the origination point of the error is corrected.

Note: A corrected read data (CRD) error interrupt is also posted in case this error is in a speculative path and the MCHK is removed. The CRD PALcode reads the status, to detect this condition, and scrubs the block. In the normal MCHK flow, the PALcode clears the pending CRD error.

8.9.2 Dcache Fill from Bcache

If the quadword in error is not used to satisfy a load instruction, a hardware recovery flow is not invoked. The quadword in error, and its associated check bits, are written into the Dcache. However, status is logged as shown in the bulleted list below, and a corrected read data (CRD) error interrupt is posted, when enabled. PALcode may elect to correct the error by scrubbing the block. If the error is not corrected by PALcode when it occurs, the error will be detected and corrected by a later load/victim operation.

If the quadword in error is used to satisfy a load instruction, then the flow is very simi- lar to that used for a Dcache ECC error. The LSD ECC checker detects the error and the 21264/EV68A performs the following actions:

•The load instruction’s destination register is written with incorrect data; however, the load queue will retain the state associated with the load instruction.

•A consumer of the load instruction’s data may be issued before the error is recognized. The Ibox will invoke a replay trap at an instruction that is older than (or equal to) any instruction that consumes the load instruction’s data. The 21264/ EV68A then stalls the replayed Istream in the map stage of the pipeline, until the error is corrected.

•With a READ_ERR read type from the Mbox for the load instruction in error, the Cbox scrubs the block in the Dcache by evicting the block into the victim buffer and writing it back into the Dcache.

•C_STAT[DSTREAM_BC_ERR] is set.

•C_ADDR contains bits [42:6] of the Bcache fill address of the block that contains the error.

•C_SYNDROME_0[7:0] and C_SYNDROME_1[7:0] contain the syndrome of quadword 0 and 1, respectively, of the octaword subblock that contains the error.

•The load queue retries the load instruction and rewrites the register.

•DC_STAT[ECC_ERR_LD] is set.

•A corrected read data (CRD) error interrupt is posted, when enabled.

8–6 Error Detection and Error Handling 21264/EV68A Hardware Reference Manual