Compaq EV68A specifications Guideline 16 JSR-BAD VA, Guideline 20 Ictlsbe Stream Buffer Enable

Guideline 16 : JSR-BAD VA

D.12 Guideline 16 : JSR-BAD VA

A JSR memory format instruction that generates a bad VA (IACV) trap requires PAL- code assistance to determine the correct exception address. If the EXC_SUM[BAD_IVA] is set, bits [63,1] of the exception address are valid in the VA IPR and not the EXC_ADDR as usual. The PALmode bit, however, is always located in EXC_ADDR[0] and must be combined, if necessary, by PALcode to determine the full exception address.

D.13 Restriction 17: MTPR to DTB_TAG0/DTB_PTE0/DTB_TAG1/ DTB_PTE1

These four write operations must be executed atomically, that is, either all four must be retired or none of them may be retired.

D.14 Restriction 18: No FP Operates, FP Conditional Branches, FTOI, or STF in Same Fetch Block as HW_MTPR

No FP operate instructions (including Mx_FPCR), FP conditional branches, FTOI reg- ister move instructions, or FP store instructions are allowed in the same fetch block as any HW_MTPR instructions. This includes ADDx/MULx/DIVx/SQRTx/FPCondition- alBranch/STx/FTOIx, where x is any applicable FP data type, but does not include LDx/ITOFx.

D.15 Restriction 19: HW_RET/STALL After Updating the FPCR by way of MT_FPCR in PALmode

FPCR updating occurs in hardware based on the retirement of a nontrapping version of MT_FPCR (in PALcode). Use a HW_RET/STALL after the nontrapping MT_FPCR to achieve minimum latency (four cycles) between the retiring of the MT_FPCR and the first FLOP that uses the updated FPCR.

D.16 Guideline 20 : I_CTL[SBE] Stream Buffer Enable

The I_CTL[SBE] bits should not be enabled when running with the Icache disabled to avoid potentially long fill delays. When the Icache is disabled, the only method of sup- plying instructions is by way of a stream hit. If the fill is returned in non-sequential wrap order, the stream will continue fetching through the entire page while waiting for a hit. Normally the data will be found in the cache.

D.17 Restriction 21: HW_RET/STALL After HW_MTPR ASN0/ASN1

There must be a scoreboard bit-to-register dependency chain to prevent HW_MTPR ASN0 or HW_MTPR ASN1 from being issued while any of scoreboard bits [7:4] are set. The following example contains a code sequence that creates the dependency chain.

:Assume Ra holds value to write to ASN0/ASN1 HW_MFPR R0, VA, SCBD<7,6,5,4>

XOR R0, R0, R0

BIS R0, R9, R9

D–12PALcode Restrictions and Guidelines 21264/EV68A Hardware Reference Manual