3–4 Hardware Interface
21264/EV68A Hardware Reference Manual
21264/EV68A SignalNames and Functions
BcDataOutClk_H[3:0]
BcDataOutClk_L[3:0] O_PP 8 Bcachedata outputclocks. These free-running clocks are dif-
ferentialcopies of the Bcache clock and are derived from the
21264/EV68AGCLK. Their period is a multiple of the GCLK
andis fixed for all operations. They can be configured so that
theirrising edge lags BcAdd_H[23:4] by 0 to 2 GCLK cycles.
The 21264/EV68Asynchronizes tag output information with
theseclocks.
BcDataWr_L O_PP 1 Bcachedata write enable. The 21264/EV68A assertsthis signal
whenwriting data to the Bcache data arrays.
BcLoad_L O_PP 1 Bcacheburst enable.
BcTag_H[42:20] B_DA_PP 23 Bcachetag bits.
BcTagDirty_H B_DA_PP 1 Tag dirty statebit. During cache write operations, the 21264/
EV68Awill assert this signal if the Bcache data has been mod-
ified.
BcTagInClk_H I_DA 1 Bcachetag input clock. The 21264/EV68A uses this input
clockto latch the tag information on Bcacheread operations.
This clock is used with high-speed SDRAMs, such as DDRs,
thatprovide a clock-out with data-output pins to optimize
Bcacheread bandwidths. The 21264/EV68A internally syn-
chronizesthe data to its logic with clock forward receivecir-
cuits similar to th e system interface.
BcTagOE_L O_PP 1 Bcachetag output enable. This signal is asserted by the 21264/
EV68Afor Bcache read operations.
BcTagOutClk_H
BcTagOutClk_L O_PP 2 Bcachetag output clock. Theseclocks “echo” the clock-for-
wardedBc DataOutClk_x[3:0] clocks.
BcTagParity_H B_DA_PP 1 Tagparity state bit.
BcTagShared_H B_DA_PP 1 Tag shared state bit. The 21264/EV68Awill write a 1 on this
signalline if another agent has a copy of the cache line.
BcTagValid_H B_DA_PP 1 Tag valid state bit. Ifset, this line indicates that thecache line
isvalid.
BcTagWr_L O_PP 1 Tag RAM write enable. The 21264/EV68Aasserts this signal
whenwriting a tag to the Bcache tag arrays.
BcVref I_DC_REF 1 Bcache tag reference voltage.
ClkFwdRst_H I_DA 1 Systems assert this synchronous signal to wake up a powered-
down21264/EV68A. The ClkFwdRst_H signal is clocked
intoa 21264/EV68A register by the captured FrameClk_x
signals.Systems must ensure that the timing of this signal
meets21264/EV68A requirements (see Section 4.7.2).
ClkIn_H
ClkIn_L I_DA_CLK 2 Differentialinput signals provided by the system.
DCOK_H I_DA 1 dc voltage OK. Must be deasserted until dc voltagereaches
properoperating level. After that, DCOK_H is asserte d.
EV6Clk_H
EV6Clk_L O_PP_CLK 2 Providesan external test point tomeasure phase alignment of
thePLL.
Table 3–2 21264/E V68AS ignal Descriptions (Continued)
Signal Type Count Description