Pipeline Organization

Figure 2–8 Pipeline Organization

0

1

2

3

4

5

6

Branch

 

 

Predictor

 

Integer

 

 

 

 

Register

 

 

Rename

 

 

Map

 

 

 

 

 

 

 

Four

 

Instructions

Instruction

 

 

 

 

Cache

 

 

(64KB)

 

Floating-

(2-Set)

 

 

Point

 

 

 

 

Register

 

 

Rename

 

 

Map

 

 

 

 

 

 

ALU

 

 

 

 

 

 

 

 

Shifter

 

 

 

 

 

 

 

Integer

 

 

ALU Shifter

Integer

 

Multiplier

Issue

 

Register

 

 

 

 

Queue

 

 

 

 

File

 

 

Address

(20)

 

ALU

 

 

 

 

 

 

 

 

 

 

 

 

Address

 

 

 

 

 

 

 

ALU

 

 

 

Floating-Point

 

 

 

 

 

 

Floating-

Floating-

 

Add, Divide,

 

and Square Root

Point

 

Point

 

 

 

 

 

Issue

 

 

 

 

Register

 

Floating-Point

Queue

 

File

 

(15)

 

Multiply

 

 

 

 

 

 

 

 

 

 

 

 

 

 

64KB

Data

Cache

 

System

 

Bus

 

(64 Bits)

Bus

 

Interface

Cache

Unit

 

Bus

 

(128 Bits)

 

Physical

 

Address

 

(44 Bits)

 

FM-05575.AI4

Stage 0 Instruction Fetch

The branch predictor uses a branch history algorithm to predict a branch instruction tar- get address.

Up to four aligned instructions are fetched from the Icache, in program order. The branch prediction tables are also accessed in this cycle. The branch predictor uses tables and a branch history algorithm to predict a branch instruction target address for one branch or memory format JSR instruction per cycle. Therefore, the prefetcher is limited to fetching through one branch per cycle. If there is more than one branch within the fetch line, and the branch predictor predicts that the first branch will not be taken, it will predict through subsequent branches at the rate of one per cycle, until it predicts a taken branch or predicts through the last branch in the fetch line.

The Icache array also contains a line prediction field, the contents of which are applied to the Icache in the next cycle. The purpose of the line predictor is to remove the pipe- line bubble which would otherwise be created when the branch predictor predicts a branch to be taken. In effect, the line predictor attempts to predict the Icache line which the branch predictor will generate. On fills, the line predictor value at each fetch line is initialized with the index of the next sequential fetch line, and later retrained by the branch predictor if necessary.

Stage 1 — Instruction Slot

The Ibox maps four instructions per cycle from the 64KB 2-way set-predict Icache. Instructions are mapped in order, executed dynamically, but are retired in order.

2–14Internal Architecture

21264/EV68A Hardware Reference Manual

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Compaq EV68A specifications Stage 0 Instruction Fetch, Stage 1 Instruction Slot, 14Internal Architecture