Compaq EV68A specifications WMB Instruction Processing

I/O Write Buffer and the WMB Instruction

2.12.1.1 MB Instruction Processing

When an MB instruction is fetched in the predicted instruction execution path, it stalls in the map stage of the pipeline. This also stalls all instructions after the MB, and con- trol of instruction flow is based upon the value in Cbox CSR SYSBUS_MB_ENABLE as follows:

•If Cbox CSR SYSBUS_MB_ENABLE is clear, the Cbox waits until the IQ is empty and then performs the following actions:

a.Sends all pending MAF and IOWB entries to the system port.

b.Monitors Cbox CSR MB_CNT[3:0], a 4-bit counter of outstanding committed events. When the counter decrements from one to zero, the Cbox marks the youngest probe queue entry.

c.Waits until the MAF contains no more Dstream references and the SQ, LQ, and IOWB are empty.

When all of the above have occurred and a probe response has been sent to the sys- tem for the marked probe queue entry, instruction execution continues with the instruction after the MB.

•If Cbox CSR SYSBUS_MB_ENABLE is set, the Cbox waits until the IQ is empty and then performs the following actions:

a.Sends all pending MAF and IOWB entries to the system port

b.Sends the MB command to the system port

c.Waits until the MB command is acknowledged, then marks the youngest entry in the probe queue

d.Waits until the MAF contains no more Dstream references and the SQ, LQ, and IOWB are empty

When all of the above have occurred and a probe response has been sent to the sys- tem for the marked probe queue entry, instruction execution continues with the instruction after the MB.

Because the MB instruction is executed speculatively, MB processing can begin and the original MB can be killed. In the internal acknowledge case, the MB may have already been sent to the system interface, and the system is still expected to respond to the MB.

2.12.1.2 WMB Instruction Processing

Write memory barrier (WMB) instructions are issued into the Mbox store-queue, where they wait until they are retired and all prior store instructions become writable. The Mbox then stalls the writable pointer and informs the Cbox. The Cbox closes the IOWB merge register and responds in one of the following two ways:

•If Cbox CSR SYSBUS_MB_ENABLE is clear, the Cbox performs the following actions:

a.Stalls further MAF and IOWB processing.

b.Monitors Cbox CSR MB_CNT[3:0], a 4-bit counter of outstanding committed events. When the counter decrements from one to zero, the Cbox marks the youngest probe queue entry.

21264/EV68A Hardware Reference Manual Internal Architecture 2–33