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Compaq EV68A specifications Risc, Rom, Rtl, Sam, Sbo, Sbz

Models: EV68A

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read stream buffers

Arrangement whereby each memory module independently prefetches DRAM data prior to an actual read request for that data. Reduces average memory latency while improving total memory bandwidth.

receive counter

Counter used to enable the receive flops. It is clocked by the incoming forwarded clock and reset by the Interface Reset.

receive mux counter

The receive mux counter is preset to a selectable starting point and incremented by the locally generated forward clock.

register

A temporary storage or control location in hardware logic.

reliability

The probability a device or system will not fail to perform its intended functions during a specified time interval when operated under stated conditions.

reset

An action that causes a logic unit to interrupt the task it is performing and go to its ini- tialized state.

RISC

Reduced instruction set computing. A computer with an instruction set that is paired down and reduced in complexity so that most can be performed in a single processor cycle. High-level compilers synthesize the more complex, least frequently used instruc- tions by breaking them down into simpler instructions. This approach allows the RISC architecture to implement a small, hardware-assisted instruction set, thus eliminating the need for microcode.

ROM

Read-only memory.

RTL

Register-transfer logic.

SAM

Serial access memory.

SBO

Should be one.

SBZ

Should be zero.

scheduling

The process of ordering instruction execution to obtain optimum performance.

Glossary–14

21264/EV68A Hardware Reference Manual

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Compaq EV68A specifications Risc, Rom, Rtl, Sam, Sbo, Sbz

Contents

Revision/Update Information Compaq Computer Corporation Shrewsbury, Massachusetts 21264/EV68A Hardware Reference Manual Table of Contents Hardware Interface Cache and External Interfaces Internal Processor Registers Privileged Architecture Library Code Initialization and Configuration Mffpcr Mtfpcr Error Detection and Error Handling Testability and DiagnosticsElectrical Data Thermal Management Alpha Instruction Set 21264/EV68A Boundary-Scan Register 21264/EV68A-to-Bcache Pin Interface Glossary Index Figures 10-2 Type 2 Heat Sink Tables Xiv VDD Idcpower Page Preface ContentAudience Documentation Included by Reference For example Terminology and ConventionsAbbreviations W1C W1SAddresses Aligned and Unaligned Signal Names Data UnitsDo Not Care External Undefined Do not care. a capital X represents any valid value Page Architecture IntroductionIntroduction Architecture AddressingInteger Data Types Floating-Point Data Types 21264/EV68A Microprocessor Features 21264/EV68A Microprocessor Features 21264/EV68A Microprocessor Features 21264/EV68A Microarchitecture Internal ArchitectureInternal Architecture 21264/EV68A Microarchitecture Instruction Fetch, Issue, and Retire UnitVirtual Program Counter Logic 21264/EV68A Block Diagram Branch Predictor Local Predictor Global Predictor Choice Predictor Instruction-Stream Translation Buffer Instruction Fetch Logic Integer Issue QueueRegister Rename Maps Floating-Point Issue Queue Hwret Exception and Interrupt Logic Integer Execution UnitRetire Logic PERR, MINxxx, MAXxxx, UNPKxx, PKxx Integer Execution Unit-Clusters 0 Floating-Point Execution Unit 10Internal Architecture Onchip Caches External Cache and System Interface Unit21264/EV68A contains two onchip primary-level caches Data Cache Memory Reference Unit12Internal Architecture Pipeline Organization Pipeline OrganizationSrom Interface Miss address file MAF Dstream translation buffer DTB Stage 1 Instruction Slot Stage 0 Instruction Fetch14Internal Architecture Stage 3 Issue Stage 2 Map Instruction Issue Rules Instruction Issue RulesPipeline Aborts Ebox and Fbox pipelines begin execution Instruction Group Definitions Instruction Name, Pipeline, and Types Ebox Slotting FTOIS, FtoitITOFS, ITOFF, Itoft Instruction Group Definitions and Pipeline Unit U U L E L U E E L L E U Instruction Latencies Instruction Class Latency in CyclesHwmfpr 20Internal Architecture Instruction Retire Rules Instruction Retire RulesMinimum Retire Latencies for Instruction Classes Retire of Operate Instructions into R31/F31 Retire of Operate Instructions into R31/F31Floating-Point Divide/Square Root Early Retire BSR/JSR Load Instructions to R31 and F31 Load Instructions to R31 and F31Prefetch with Modify Intent LDS Instruction Instructions Retired Without Execution Special Cases of Alpha Instruction Execution Special Cases of Alpha Instruction ExecutionPrefetch, Evict Next LDQ and Hwldq Instructions Load Hit Speculation 10 Pipeline Timing for Floating-Point Load Instructions Cmov Instruction Floating-Point Store Instructions26Internal Architecture Memory and I/O Address Space Instructions Memory and I/O Address Space InstructionsMemory Address Space Load Instructions 2 I/O Address Space Load Instructions Rules for I/O Address Space Load Instruction Data Merging Memory Address Space Store Instructions28Internal Architecture 4 I/O Address Space Store Instructions Rules for I/O Address Space Store Instruction Data Merging Instruction Ordering MAF Memory Address Space Merging RulesMAF Memory Address Space Merging Rules Replay Traps Replay TrapsMbox Order Traps 12 I/O Write Buffer and the WMB Instruction Write Buffer and the WMB InstructionOther Mbox Replay Traps Memory Barrier MB/WMB/TB Fill Flow MB Instruction Processing WMB Instruction Processing TB Fill Flow 12 TB Fill Flow Example Sequence13 TB Fill Flow Example Sequence 34Internal Architecture Performance Measurement Support-Performance Counters Floating-Point Control RegisterPerformance Measurement Support-Performance Counters Floating-point control register Fpcr is shown in Figure 14 Floating-Point Control Register Fields Floating-Point Control Register36Internal Architecture Amask and Implver Instruction Values Amask and Implver Instruction Values Design Examples Design ExamplesAmask Implver 12 Typical Uniprocessor Configuration Page Hardware Interface 21264/EV68A Microprocessor Logic SymbolHardware Interface 21264/EV68A Microprocessor Logic Symbol 21264/EV68A Microprocessor Logic Symbol 21264/EV68A Signal Names and Functions 21264/EV68A Signal Names and FunctionsSignal Pin Types Definitions 21264/EV68A Signal Descriptions Dcokh Pllvdd 21264/EV68A Signal Descriptions by Function TestStatH SysVref Domain SysAddInL140 Pin Assignments Pin List Sorted by Signal NamePin Assignments AC1 10Hardware Interface Pllvdd AA5 Pin List Sorted by PGA Location 12Hardware Interface SysDataL28 14Hardware Interface BcDataH70 SysDataL5 Ground and Power VSS and VDD Pin List 16Hardware Interface Mechanical Specifications Mechanical Specifications 21264/EV68A Packaging 21264/EV68A Packaging18Hardware Interface 21264/EV68A Bottom View Pin Up Page Introduction to the External Interfaces Cache and External InterfacesCache and External Interfaces Introduction to the External Interfaces System Interface 21264/EV68A System and Bcache Interfaces Commands and Addresses Physical Address ConsiderationsPhysical Address Considerations Second-Level Cache Bcache Interface ECB I/O MB/WMB Physical Address Considerations Bcache Interface Signals Bcache StructureBcache Structure System Duplicate Tag Stores Victim Data Buffer Cache CoherencyVictim Data Buffer Cache Coherency Basics Cache Coherency Cache Block States2lists the cache block states supported by the 21264/EV68A 21264/EV68A-Supported Cache Block States Mands. -4lists these commands System Responses to 21264/EV68A CommandsCache Block State Transitions Cache Block State Transitions Using SysDc Commands System Responses to 21264/EV68A Commands and Reactions 12Cache and External Interfaces Dcache States and Duplicate Tags Lock Mechanism Lock Mechanism14Cache and External Interfaces Internal Eviction of LDxL Blocks In-Order Processing of LDxL/STxC InstructionsLiveness and Fairness System Port System Port16Cache and External Interfaces System Port Pins System Port Pins Programming the System Interface Clocks Programming Values for System Interface ClocksProgram Values for Data-Sample/Drive CSRs 18Cache and External Interfaces Bank Interleave on Cache Block Boundary Mode 3 21264/EV68A-to-System CommandsForwarded Clocks and Frame Clock Ratio Hit Mode 11 Page Hit Mode of Operation12 21264/EV68A-to-System Command Fields Definitions 12describes the field definitions for Tables 4-10and 4 21264/EV68A-to-System Commands Descriptions 14describes the 21264/EV68A-to-system commands14 21264/EV68A-to-System Commands Descriptions 13 Maximum Physical Address for Short Bus Format 22Cache and External Interfaces 15 Programming INVALTODIRTYENABLE10 ProbeResponse Commands Command40 = 16 Programming SETDIRTYENABLE2017 21264/EV68A ProbeResponse Command 24Cache and External Interfaces 18describes the ProbeResponse command fields SysAck and 21264/EV68A-to-System Commands Flow Control18 ProbeResponse Fields Descriptions System-to-21264/EV68A Commands Probe Commands Four Cycles19 System-to-21264/EV68A Probe Commands RVB RPB 20 System-to-21264/EV68A Probe Commands Fields Descriptions 21 lists the data movement selected by Probe4322lists the next cache block state selected by Probe20 21 Data Movement Selection by Probe43 23 Data Transfer Command Format Data Transfer Commands Two Cycles28Cache and External Interfaces 24describes the SysDc40 field 24 SysDc40 Field Description 8.1 21264/EV68A Clock Basics Data Movement In and Out of the 21264/EV68A30Cache and External Interfaces Fast Data Mode 25 Sysclk Cycles Between SysAddOut and SysData 32Cache and External Interfaces 26 Cbox CSR SYSDCDELAY40 Examples 26shows four example configurations and shows their useFast Data Disable Mode 27 Four Timing Examples SysDataInValidL and SysDataOutValidLSysDataInValidL 34Cache and External Interfaces SysDataOutValidL SysFillValidL 28 Data Wrapping Rules Data Wrapping36Cache and External Interfaces 29 System Wrap and Deliver Data 30defines the interleaved scheme for the wrap order30 Wrap Interleave Order Nonexistent Memory Processing 31defines the wrap order for double-pumped data trans fers31 Wrap Order for Double-Pumped Data Transfers 38Cache and External Interfaces 21264/EV68A Command NXM Address System/21264/EV68A Response Ordering of System Port Transactions 10.1 21264/EV68A Commands and System Probes40Cache and External Interfaces System Port Bcache Port Bcache Port 36 Bcache Port Pins Bcache Port Pins35 Range of Maximum Bcache Clock Ratios Bcache Clocking 44Cache and External Interfaces 38 BCCLKDELAY10 Values 37 BCCPUCLKDELAY10 ValuesSetting the Period of the Cache Clock 39 Program Values to Set the Cache Clock Period Single-Data 46Cache and External Interfaces 41 Data-Sample/Drive Cbox CSRs Bcache TransactionsBcache Data Read and Tag Read Transactions Bcache Data Write Transactions 48Cache and External Interfaces When the ratio is even, bcfrm is equal to the ratio When the ratio is odd, bcfrm is twice the ratioFor example, in single-data mode Dual-data mode, bcfrm is twice the ratio Pin Descriptions Relationship Between Write-to-Read Bcwrrdbubbles and wrrdRelationship Between Read-to-Write Bcrdwrbubbles and rdwr 50Cache and External Interfaces Bcache Control Pins 43 Programming the Bcache Control Pins44 lists the combination of control pin assertion for BcAddH234 45 Control Pin Assertion for Ramtype B 46 Control Pin Assertion for Ramtype C47 Control Pin Assertion for Ramtype D 52Cache and External Interfaces Disabling the Bcache for Debugging Bcache BankingBcDataInClkH and BcTagInClkH Interrupts Interrupts54Cache and External Interfaces Internal Processor Registers Internal Processor Registers Mbox IPRs Ebox IPRs Ebox IPRsCycle Counter Register CC Cycle Counter Control Register Ccctl Virtual Address Register VA Virtual Address Control Register Vactl2describes the Ccctl register fields Cycle Counter Control Register Fields Description Virtual Address Format Register Vaform 3describes the virtual address control register fieldsVirtual Address Control Register Fields Description VAFORM32 Ibox IPRs Ibox IPRsITB Tag Array Write Register Itbtag ITB PTE Array Write Register Itbpte ITB Invalidate All Register Itbia ITB Invalidate All Process ASM=0 Register ItbiapITB Invalidate Single Register Itbis ProfileMe PC Register Pmpc Exception Address Register Excaddr4describes the ProfileMe PC register fields ProfileMe PC Fields Description Interrupt Enable and Current Processor Mode Register Iercm Instruction Virtual Address Format Register Ivaform Iercm Register Fields Description Software Interrupt Request Register Sirr10Internal Processor Registers 6describes the software interrupt request register fields Interrupt Summary Register IsumSoftware Interrupt Request Register Fields Description Hardware Interrupt Clear Register Hwintclr 7describes the interrupt summary register fieldsInterrupt Summary Register Fields Description 12Internal Processor Registers Exception Summary Register Excsum 8describes the hardware interrupt clear register fieldsHardware Interrupt Clear Register Fields Description Mchkd W1C Exception Summary Register Fields Description 9describes the exception summary register fields14Internal Processor Registers PAL Base Register Palbase Ibox Control Register Ictl10describes the PAL base register fields 10 PAL Base Register Fields Description 11 Ibox Control Register Fields Description 11describes the Ibox control register fields16Internal Processor Registers Singleissueh STWAIT64KPCT1EN PCT0EN Spce Ibox Status Register Istat18Internal Processor Registers 12describes the Ibox status register fields 12 Ibox Status Register Fields DescriptionMIS TRP 20Internal Processor Registers Sleep Mode Register Sleep Icache Flush Register IcflushIcache Flush ASM Register Icflushasm Clear Virtual-to-Physical Map Register Clrmap 14 Process Context Register Fields Description 14describes the process context register fields22Internal Processor Registers 15describes the performance counter control register fields Performance Counter Control Register Pctrctl15 Performance Counter Control Register Fields Description Pctxppce PmstalledPmkilledbm SL0 Mbox IPRs Mbox IPRsDTB Tag Array Write Registers 0 and 1 DTBTAG0, DTBTAG1 16 Performance Counter Control Register Input Select Fields DTB Alternate Processor Mode Register Dtbaltmode 17 DTB Alternate Processor Mode Register Fields DescriptionDTB PTE Array Write Registers 0 and 1 DTBPTE0, DTBPTE1 17describes the Dtbaltmode register fields Dstream TB Invalidate All Process ASM=0 Register Dtbiap Dstream TB Invalidate All Register DtbiaDstream TB Invalidate Single Registers 0 and 1 DTBIS0,1 ALTMODE10 Dstream TB Address Space Number Registers 0 and 1 DTBASN0,1 Memory Management Status Register Mmstat18describes the memory management status register fields 18 Memory Management Status Register Fields Description For Mbox Control Register MctlACV Erences to superpages result in access violations Dcache Control Register Dcctl19describes the Mbox control register fields 19 Mbox Control Register Fields Description 20describes the Dcache control register fields Dcache Status Register Dcstat20 Dcache Control Register Fields Description Cbox CSRs and IPRs Cbox CSRs and IPRs21describes the Dcache status register fields 21 Dcache Status Register Fields Description Cbox Data Register Cdata Cbox Shift Register CshftCbox Writeonce Chain Description 22 describes the Cbox data register fields 24 Cbox Writeonce Chain Order 34Internal Processor Registers BCWRRDBUBBLES03 Mboxbcprbstall BCLATDATAPATTERN031 BCLATTAGPATTERN023 36Internal Processor Registers SYSCLKDELAY10 Cbox Writemany Chain Description 38Internal Processor Registers 25 Cbox Writemany Chain Order 40Internal Processor Registers Cbox Read Register IPR Description 26 Cbox Read IPR Fields Description 0 1 1 Dstreammemerr 0 1 1 Istreammemerr PALcode Description Privileged Architecture Library CodePrivileged Architecture Library Code PALmode Environment PALmode Environment Required PALcode Function Codes Opcodes Reserved for PALcodeRequired PALcode Function Codes Hwld Instruction Opcodes Reserved for PALcode Hwst Instruction3describes the Hwld instruction fields Hwld Instruction Fields Descriptions 4describes the Hwst instruction fields Hwret InstructionHwst Instruction Fields Descriptions Hwmfpr and Hwmtpr Instructions 5describes the Hwret instruction fieldsHwret Instruction Fields Descriptions Hint Internal Processor Register Access Mechanisms Internal Processor Register Access Mechanisms6describes the Hwmfpr and Hwmtpr instructions fields Hwmfpr and Hwmtpr Instructions Fields Descriptions IPR Scoreboard Bits Hardware Structure of Explicitly Written IPRs Hardware Structure of Implicitly Written IPRs IPR Access OrderingPaired Instruction Fetch Order 10Privileged Architecture Library Code PALcode Emulation of the Fpcr PALshadow RegistersPALshadow Registers PALcode Entry Points PALcode Entry Points PALcode Exception Entry Points PALcode Exception Entry Locations Translation Buffer TB Fill Flows Translation Buffer TB Fill FlowsDTB Fill 14Privileged Architecture Library Code Tb miss Wr DataWr PTE LD-PTE, write TB ITB Fill 16Privileged Architecture Library Code Performance Counter Support Performance Counter Support General Precautions Aggregate Mode Programming GuidelinesAggregate Mode Precautions IPRs Used for Performance Counter Support 10 Aggregate Mode Returned IPR Contents OperationPctrctl SL0 SL1 11shows the counter modes that are used with Aggregate mode ProfileMe Mode Programming GuidelinesThis input counts Mbox replay traps 12 Cmov Decomposed 13 ProfileMe Mode Returned IPR Contents 22Privileged Architecture Library Code ProfileMe Counting Mode Description Cycle counting Inum retire delay cycles 14shows the counter modes that are used with ProfileMe mode Counter Modes for ProfileMe Mode14 ProfileMe Mode Pctrctl Input Select Fields 24Privileged Architecture Library Code Initialization and Configuration Power-Up Reset Flow and the ResetL and Dcokh Pins21264/EV68A Reset State Machine Major Operations Initialization and Configuration Power-Up Reset Flow and the ResetL and Dcokh Pins Constraints Power Sequencing and Reset State for Signal Pins Signal Pin Reset State Clock Forwarding and System Clock Ratio Configuration Pllvdd Pin Signal Names and Initialization State PLL PLL Ramp Up BiST and Srom Load and the TestStatH Pin Power-Up Flow Signals and Their Constraints Clock Forward Reset and System Interface InitializationEV68A Fault Reset Flow Fault Reset FlowEffect on IPRs After Fault Reset Energy Star Certification and Sleep Mode Flow Energy Star Certification and Sleep Mode Flow Effect on IPRs After Transition Through Sleep Mode 10Initialization and Configuration Warm Reset Flow Warm Reset FlowSignals and Constraints for the Sleep Mode Sequence Effect on IPRs After Warm Reset Initialization Mode Processing 12Initialization and ConfigurationArray Initialization Array Initialization Initialization Mode Processing Evictenable BCWRTSTS30 Bcbankenable Internal Processor Register Power-Up Reset State 10 Internal Processor Registers at Power-Up Reset State14Initialization and Configuration External Interface Initialization Internal Processor Register Power-Up Reset State Ieee 1149.1 Test Port Reset Reset State MachineIeee 1149.1 Test Port Reset 16Initialization and Configuration Reset State Machine 11 21264/EV68A Reset State Machine State Descriptions 18Initialization and Configuration Phase-Lock Loop PLL Functional Description Phase-Lock Loop PLL Functional DescriptionDifferential Reference Clocks PLL Output Clocks Power-Up/Reset Clocking 20Initialization and Configuration 21264/EV68A Error Detection Mechanisms Error Detection and Error HandlingError Detection and Error Handling Data Error Correction Code Icache Data or Tag Parity ErrorDcache Tag Parity Error Data Error Correction Code Dcache Data Single-Bit Correctable ECC Error Dcache Data Single-Bit Correctable ECC ErrorLoad Instruction Dcache Store Second Error Dcache Duplicate Tag Parity ErrorDcache Store Second Error Store Instruction Quadword or Smaller Bcache Tag Parity Error Bcache Data Single-Bit Correctable ECC ErrorBcache Tag Parity Error Controlling Bcache Block Parity Calculation Bcache Data Single-Bit Correctable ECC Error Dcache Fill from Bcache Memory/System Port Single-Bit Data Correctable ECC Error Memory/System Port Single-Bit Data Correctable ECC ErrorBcache Victim Read Icache Fill from Memory Dcache Fill from Memory Double-Bit Fill Errors Bcache Data Single-Bit Correctable ECC Error on a ProbeBcache Data Single-Bit Correctable ECC Error on a Probe Error Case Summary Error Case Summary3summarizes the various error cases and their ramifications Section D.36 Mchk Cstatistreammemerr CstatdstreammemerrCRD Cstatprobebcerr Mchk CstatistreambcdblPage Electrical Characteristics Electrical Data1lists the maximum electrical ratings for the 21264/EV68A Maximum Electrical Ratings DC Characteristics DC CharacteristicsSignal Types Idcpower VDD Idcpower Input DC Reference Pin IdcrefInput Differential Amplifier Receiver IDA Input Differential Amplifier Clock Receiver Idaclk Pin Type Open-Drain Driver for Test Pins Oodtp Pin Type Open-Drain Output Driver OODIOZ Codtp 11 Push-Pull Output Driver OPP 12 Push-Pull Output Clock Driver Oppclk AC Characteristics AC CharacteristicsAC Test Conditions 13 AC Specifications TSU1 TDH2 Dcokh AC Characteristics Page Operating Temperature Operating Temperature at Heat Sink Center TcThermal Management That causes thermal failure Θca at Various Airflows for 21264/EV68A Operating Temperature10-2Thermal Management Heat Sink Specifications Heat Sink Specifications Type 2 Heat Sink 10-4Thermal Management Type 3 Heat Sink Thermal Design Considerations Thermal Design Considerations10-6Thermal Management Testability and Diagnostics Test PinsDedicated Test Port Pins Testability and Diagnostics SROM/Serial Diagnostic Terminal Port SROM/Serial Diagnostic Terminal Port11-2Testability and Diagnostics Srom Load Operation Ieee 1149.1 Port Ieee 1149.1 PortIeee 1149.1 Instructions and Opcodes 11-4Testability and Diagnostics TestStatH PinTestStatH Pin TAP Controller State Machine Power-Up Self-Test and Initialization Power-Up Self-Test and InitializationBuilt-in Self-Test Srom Initialization 11-6Testability and Diagnostics Serial Instruction Cache Load Operation Icache Bit Fields in an Srom Line See Appendix B for a listing of the Boundary-Scan RegisterReferences Page Alpha Instruction Set Alpha Instruction SummaryTable A-1 Instruction Format and Opcode Notation Alpha Instruction Set A-1 Alpha Instruction Summary Mbr Branch to subroutine Pcd Trap to PALcodeOpr 11.24 Cmove if = zero Opr 11.46 Cmove if ≥ zero 15.0AF Convert Gfloating to quadword 17.010 Convert longword to quadword15.0BC Convert quadword to Ffloating 15.0BE Convert quadword to Gfloating 17.02F Fcmove if zero 17.02E Fcmove if ≤ zero17.02C Fcmove if zero 17.02B Fcmove if ≠ zero Opr 13.40 Multiply longword with integer overflow enable Opr 13.60 Multiply quadword with integer overflow enableOpr 1C.31 Pixel error Mem Load Sfloating Opr 1C.36 Pack words to bytes Mfc 18.E000 Read and clear Mbr 1A.2 Return from subroutineMfc 18.C000 Read process cycle counter 18.F000 Read and set Opr 10.02 Scaled add longword by Reserved Opcodes Reserved OpcodesOpcodes Reserved for Compaq Ieee Floating-Point Instructions Ieee Floating-Point InstructionsOpcodes Reserved for PALcode 08B 00B 04B 18B 10B 14B02B 06B 12B 16B Independent Floating-Point Instructions VAX Floating-Point InstructionsVAX Floating-Point Instructions Opcode Summary Opcode Summary Mem Table A-9explains the symbols used in Table A-8 Mem ResIeee floating-point instruction opcodes Floating-point operate instruction opcodes Ieee Floating-Point Conformance Ieee Floating-Point Conformance14Alpha Instruction Set Table A-11 Exceptional Input and Output Conditions Alpha Instruction Set A-15 16Alpha Instruction Set Cmptlt Cmptle Input Cmpteq Cmptun InputAlpha Instruction Set A-17 Fbeq Fbne Fblt Fble Fbgt Fbge LDS LDT STS STT Cpys Cpysn 21264/EV68A Boundary-Scan Register Boundary-Scan Register Boundary-Scan Register Pllvdd 21264/EV68A Boundary-Scan Register B-3 421264/EV68A Boundary-Scan Register 21264/EV68A Boundary-Scan Register B-5 621264/EV68A Boundary-Scan Register 21264/EV68A Boundary-Scan Register B-7 821264/EV68A Boundary-Scan Register 21264/EV68A Boundary-Scan Register B-9 1021264/EV68A Boundary-Scan Register 21264/EV68A Boundary-Scan Register B-11 1221264/EV68A Boundary-Scan Register Serial Icache Load Predecode Values Serial Icache Load Predecode Values C-1Page PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-1 2PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-3 4PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-5 Initwritemany 6PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-7 8PALcode Restrictions and Guidelines Restriction 7 Replay Trap, Interrupt Code Sequence, and STF PALcode Restrictions and Guidelines D-9 Restriction 10 Duplicate IPR Mode Bits Restriction 9 PALmode Istream Address RangesRestriction 9 PALmode Istream Address Ranges 10PALcode Restrictions and Guidelines Restriction 11 Ibox IPR Update Synchronization Restriction 11 Ibox IPR Update SynchronizationRestriction 13 DTB Fill Flow Collision Restriction 14 Hwret Guideline 20 Ictlsbe Stream Buffer Enable Guideline 16 JSR-BAD VARestriction 21 HWRET/STALL After Hwmtpr ASN0/ASN1 Guideline 16 JSR-BAD VA Restriction 22 HWRET/STALL After Hwmtpr IS0/IS1 Restriction 22 HWRET/STALL After Hwmtpr IS0/IS1PALcode Restrictions and Guidelines D-13 Restriction 25 Hwmtpr Itbia After Reset Guideline 26 Conditional Branches in PALcodeRestriction 24 HWRET/STALL After Hwmtpr ICFLUSH, Icflushasm 14PALcode Restrictions and Guidelines Restriction 30 Hwmtpr and Hwmfpr to the Cbox CSR Guideline 29 JSR, JMP, RET, and Jsrcor in PALcodePALcode Restrictions and Guidelines D-15 Restriction 30 Hwmtpr and Hwmfpr to the Cbox CSR 16PALcode Restrictions and Guidelines Restriction 31 ICTLVA48 Update Restriction 32 Pctrctl UpdateRestriction 31 ICTLVA48 Update PALcode Restrictions and Guidelines D-17 Guideline 35 Hwintclr Update Restriction 33 Hwld Physical/Lock UseRestriction 36 Updating Ictlsde Restriction 37 Updating VACTLVA48 Restriction 40 Scrubbing a Single-Bit Error PALcode Restrictions and Guidelines D-19 Restriction 40 Scrubbing a Single-Bit Error 20PALcode Restrictions and Guidelines Restriction 43 No Trappable Instructions Along with Restriction 42 Updating VACTL, CCCTL, or CC IPRsPALcode Restrictions and Guidelines D-21 Restriction 47 Cache Eviction for Single-Bit Cache Errors 22PALcode Restrictions and Guidelines Restriction 47 Cache Eviction for Single-Bit Cache Errors PALcode Restrictions and Guidelines D-23 24PALcode Restrictions and Guidelines Forwarding Clock Pin Groupings 21264/EV68A-to-Bcache Pin InterfaceTable E-1 Bcache Forwarding Clock Pin Groupings Late-Write Non-Bursting SSRAMs Late-Write Non-Bursting SSRAMsData Pin Usage Tag Pin Usage Dual-Data Rate SSRAMs Dual-Data Rate SSRAMsTable E-4 Dual-Data Rate Ssram Data Pin Usage Table E-5 Dual-Data Rate Ssram Tag Pin Usage Trstl421264/EV68A-to-Bcache Pin Interface 21264/EV68A-to-Bcache Pin Interface E-5 Page Glossary BIU BSR Cisc Cmos CPICPU CSR DMA DramDTB DTL Feprom FETFEU Fpga Gclk IDU Iowb IpgaITB Jfet MAF MBOMBZ Mips MSI Naturally AlignedNmos Nvram PAL PGAPLA Plcc Pqfp PromRAM RAS Risc ROMRTL SAM Sdram SimmSIP Sipp Stram TTLUart Unaligned Unpredictable UvpromVAF VDF WAR Writeblock Index Numerics Index-2 Index-3 Index-4 ECC Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12