Compaq EV68A specifications MAF Memory Address Space Merging Rules, Instruction Ordering

MAF Memory Address Space Merging Rules

2.9 MAF Memory Address Space Merging Rules

Because all memory transactions are to 64-byte blocks, efficiency is improved by merg- ing several small data transactions into a single larger data transaction. Table 2–9lists the rules the 21264/EV68A uses when merging memory transactions into 64-byte natu- rally aligned data block transactions. Rows represent the merged instruction in the MAF and columns represent the new issued transaction.

Table 2–9 MAF Merging Rules

MAF/New	LDx	STx	STx_C	WH64		ECB	Istream
LDx	Merge	—	—	—	—	—
STx	Merge	Merge	—	—	—	—
STx_C	—	—	Merge	—	—	—
WH64	—	—	—	Merge	—	—
ECB	—	—	—	—	Merge	—
Istream	—	—	—	—	—	Merge

In summary, Table 2–9shows that only like instruction types, with the exception of load instructions merging with store instructions, are merged.

2.10 Instruction Ordering

In the absence of explicit instruction ordering, such as with MB or WMB instructions, the 21264/EV68A maintains a default instruction ordering relationship between pairs of load and store instructions.

The 21264/EV68A maintains the default memory data instruction ordering as shown in Table 2–10(assume address X and address Y are different).

Table 2–10 Memory Reference Ordering

First Instruction in Pair Second Instruction in Pair Reference Order

Load memory to address X Load memory to address X Store memory to address X Store memory to address X Load memory to address X Load memory to address X Store memory to address X Store memory to address X

Load memory to address X	Maintained (litmus test 1)
Load memory to address Y	Not maintained
Store memory to address X	Maintained
Store memory to address Y	Maintained
Store memory to address X	Maintained
Store memory to address Y	Not maintained
Load memory to address X	Maintained
Load memory to address Y	Not maintained

2–30Internal Architecture 21264/EV68A Hardware Reference Manual