Compaq EV68A specifications Index-2

BC_SJ_BANK_ENABLE Cbox CSR

defined, 5–34

BC_TAG_DDM_FALL_EN Cbox CSR, 4–47

defined, 5–36

BC_TAG_DDM_RISE_EN Cbox CSR, 4–47

defined, 5–36

BC_WR_RD_BUBBLES Cbox CSR, 4–49

defined, 5–35

BC_WR_WR_BUBBLE Cbox CSR, 4–53

defined, 5–34

BC_WRT_STS Cbox CSR, 5–39 ,7–13

Bcache

banking, 4–53

bubbles on the data bus, 4–49clocking, 4–44

control pins, 4–51

data read transactions, 4–47

data single-bit correctable ECC error, 8–5

data single-bit correctable ECC error on a probe, 8–9

data write transactions, 4–48error case summary for, 8–10filling Dcache error, 8–6filling Icache error, 8–5forwarding clock pin groupings, E–1maximum clock ratio, 4–42

port, 4–42port pins, 4–43

programming the size of, 4–51setting clock period, 4–45structure of, 4–7

tag parity errors, 8–5

tag read transactions, 4–47

victim read during an ECB instruction error, 8–7

victim read during Dcache/Bcache miss error, 8–7

victim read error, 8–7BcAdd_H signal pins, 3–3 ,4–43

characteristics, 4–51BcCheck_H signal pins, 3–3 ,4–43BcData_H signal pins, 3–3 ,4–43

BcDataInClk_H signal pins, 3–3 ,4–43using, 4–53

BcDataOE_L signal pin, 3–3 ,4–43BcDataOutClk_x signal pins, 3–4 ,4–43

BcDataWr_L signal pin, 3–4 ,4–44

BcLoad_L signal pin, 3–4 ,4–44

BcTag_H signal pins, 3–4 ,4–44

BcTagDirty_H signal pin, 3–4 ,4–44

BcTagInClk_H signal pin, 3–4 ,4–44using, 4–53

BcTagOE_L signal pin, 3–4 ,4–44BcTagOutClk_x signal pins, 3–4 ,4–44

BcTagParity_H signal pin, 3–4 ,4–44

BcTagShared_H signal pin, 3–4 ,4–44BcTagValid_H signal pin, 3–4 ,4–44

BcTagWr_L signal pin, 3–4 ,4–44

BcVref signal pin, 3–4 ,4–44

Bidirectional differential amplifier receiver - open-drain. See B_DA_OD

Bidirectional differential amplifier receiver - push-pull. See B_DA_PP

Binary multiple abbreviations, xix

BiST. See Built-inself-test

Bit notation conventions, xx

Bounder-scan register, B–1

Branch history table, initialized by BiST, 7–12

Branch mispredication, pipeline abort delay from, 2–16

Branch predictor, 2–3

BSDL description of the boundary-scan register, B–1

Built-in self-test,11–5load, 7–6

C

C_ADDR Cbox read register field, 5–42

C_DATA Cbox data register, 5–33at power-on reset state, 7–16

C_SHFT Cbox shift register, 5–33at power-on reset state, 7–16

C_STAT Cbox read register field, 5–42

C_STS Cbox read register field, 5–42

C_SYNDROME_0 Cbox read register field, 5–41

C_SYNDROME_1 Cbox read register field, 5–41

Cache block states, 4–9

response to 21264/EV68A commands, 4–10transitions, 4–10

Cache coherency, 4–8

CALL_PAL entry points, 6–12Caution convention, xx

Index–2 21264/EV68A Hardware Reference Manual