Compaq EV68A Required PALcode Function Codes, Opcodes Reserved for PALcode, Hwld Instruction

Required PALcode Function Codes

When executing in PALmode, there are certain restrictions for using the privileged instructions because PALmode gives the programmer complete access to many of the internal details of the 21264/EV68A. Refer to Section 6.4 for information on these spe- cial PALmode instructions.

Caution: It is possible to cause unintended side effects by writing what appears to be perfectly acceptable PALcode. As such, PALcode is not something that many users will want to change. Before writing PALcode, at least become familiar with the information in Appendix D.

6.3 Required PALcode Function Codes

Table 6–1lists opcodes required for all Alpha implementations. The notation used is oo.ffff, where oo is the hexadecimal 6-bit opcode and ffff is the hexadecimal 26-bit function code.

Table 6–1 Required PALcode Function Codes

Mnemonic	Type	Function Code
DRAINA	Privileged	00.0002
HALT	Privileged	00.0000
IMB	Unprivileged	00.0086

6.4 Opcodes Reserved for PALcode

Table 6–2lists the opcodes reserved by the Alpha architecture for implementation-spe- cific use. These opcodes are privileged and are only available in PALmode.

Table 6–2 Opcodes Reserved for PALcode

		Architecture
Mnemonic	Opcode	Mnemonic	Function
HW_LD	1B	PAL1B	Dstream load instruction
HW_ST	1F	PAL1F	Dstream store instruction
HW_RET	1E	PAL1E	Return from PALcode routine
HW_MFPR	19	PAL19	Copies the value of an IPR into an integer GPR
HW_MTPR	1D	PAL1D	Writes the value of an integer GPR into an IPR

These instructions generally produce an OPCDEC exception if executed while the pro- cessor is not in PALmode. If I_CTL[HWE] is set, these instructions can also be exe- cuted in kernel mode. Software that uses these instructions must adhere to the PALcode restrictions listed in this section.

6.4.1 HW_LD Instruction

PALcode uses the HW_LD instruction to access memory outside the realm of normal Alpha memory management and to perform special Dstream load transactions. Data alignment traps are disabled for the HW_LD instruction.

Figure 6–1shows the HW_LD instruction format.

21264/EV68A Hardware Reference Manual Privileged Architecture Library Code 6–3