Compaq specifications 21264/EV68A Microprocessor Features

21264/EV68A Microprocessor Features

1.2 21264/EV68A Microprocessor Features

The 21264/EV68A microprocessor is a superscalar pipelined processor. It is packaged in a 587-pin PGA carrier and has removable application-specific heat sinks. A number of configuration options allow its use in a range of system designs ranging from extremely simple uniprocessor systems with minimum component count to high-per- formance multiprocessor systems with very high cache and memory bandwidth.

The 21264/EV68A can issue four Alpha instructions in a single cycle, thereby minimiz- ing the average cycles per instruction (CPI). A number of low-latency and/or high- throughput features in the instruction issue unit and the onchip components of the mem- ory subsystem further reduce the average CPI.

The 21264/EV68A and associated PALcode implements IEEE single-precision and double-precision, VAX F_floating and G_floating data types, and supports longword (32-bit) and quadword (64-bit) integers. Byte (8-bit) and word (16-bit) support is pro- vided by byte-manipulation instructions. Limited hardware support is provided for the VAX D_floating data type.

Other 21264/EV68A features include:

•The ability to issue up to four instructions during each CPU clock cycle.

•A peak instruction execution rate of four times the CPU clock frequency.

•An onchip, demand-paged memory-management unit with translation buffer, which, when used with PALcode, can implement a variety of page table structures and trans- lation algorithms. The unit consists of a 128-entry, fully-associative data translation buffer (DTB) and a 128-entry, fully-associative instruction translation buffer (ITB), with each entry able to map a single 8KB page or a group of 8, 64, or 512 8KB pages. The allocation scheme for the ITB and DTB is round-robin. The size of each translation buffer entry’s group is specified by hint bits stored in the entry. The DTB and ITB implement 8-bit address space numbers (ASN), MAX_ASN=255.

•Two onchip, high-throughput pipelined floating-point units, capable of executing both VAX and IEEE floating-point data types.

•An onchip, 64KB virtually-addressed instruction cache with 8-bit ASNs (MAX_ASN=255).

•An onchip, virtually-indexed, physically-tagged dual-read-ported, 64KB data cache.

•Supports a 48-bit or 43-bit virtual address (program selectable).

•Supports a 44-bit physical address.

•An onchip I/O write buffer with four 64-byte entries for I/O write transactions.

•An onchip, 8-entry victim data buffer.

•An onchip, 32-entry load queue.

•An onchip, 32-entry store queue.

•An onchip, 8-entry miss address file for cache fill requests and I/O read transactions.

•An onchip, 8-entry probe queue, holding pending system port probe commands.

21264/EV68A Hardware Reference Manual Introduction 1–3