Compaq EV68A specifications DTB PTE Array Write Registers 0 and 1 DTBPTE0, DTBPTE1

Mbox IPRs

5.3.2 DTB PTE Array Write Registers 0 and 1 – DTB_PTE0, DTB_PTE1

The DTB PTE array write registers 0 and 1 (DTB_PTE0 and DTB_PTE1) are registers through which the DTB PTE arrays are written. The entries to be written are chosen by

around-robin allocation scheme. Write transactions to the DTB_PTE registers, when retired, result in both the DTB_TAG and DTB_PTE arrays being written. Figure 5–27shows the DTB PTE array write registers 0 and 1.

Figure 5–27 DTB PTE Array Write Registers 0 and 1

63 62 32 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PA[43:13]

UWE

SWE

EWE

KWE

URE

SRE

ERE

KRE

GH[1:0]

ASM

FOW

FOR

LK99-0036A

5.3.3 DTB Alternate Processor Mode Register – DTB_ALTMODE

The DTB alternate processor mode register (DTB_ALTMODE) is a write-only register whose contents specify the alternate processor mode used by some HW_LD and HW_ST instructions. Figure 5–28shows the DTB alternate processor mode register.

Figure 5–28 DTB Alternate Processor Mode Register

63 2 1 0

ALT_MODE[1:0]

LK99-0037A

Table 5–17describes the DTB_ALTMODE register fields.

Table 5–17 DTB Alternate Processor Mode Register Fields Description

Name	Extent	Type	Description
Reserved	[63:2]	—	—

5–26Internal Processor Registers 21264/EV68A Hardware Reference Manual