4–14 Cache and External Interfaces
21264/EV68A Hardware Reference Manual

Lock Mechanism

1. When theMbox requests a Dcache fill, the Cbox uses the CTAG array entryto find
if the Dcachea lreadycontains the requested physical address in another virtually-
indexedDc acheline. If it does, the Cbox invalidates that cache line after first writ-
ingthe data back to the Bcache if it was in the modified state. The Cbox also checks
to see if the Dcache contains an address different from the reques ted address, but
mapsto the same Bcache line.If it does, the Dcache line is evicted in order to keep
the Dcachea subset of the Bcache.
2. Whenthe Ibox requests an Icache fill, the Cbox uses the CTAG arrayentries to find
if the Dcachecontains the requested physical address in the modified state.I fit
does,the Cbox forces the line to be written back to the Bcache before servicing the
Icache fillrequest. The Cbox also checks to see if the Dcache contains an address
different from the requested address but which maps to the same Bcache line. In
thisc ase theIstream request will miss the Bcache, and the Cbox will
servicethe request by launching a noncached Fetch command to the system port
and will not put theI streamblock into the Bcache. This mechanism allows the
21264/EV68Ato use a cache resident lockflag for LDx_L/STx_C instructions.
3. The Cbox uses the CTAGarray entries to find whether probe addresses are held in
the Dcachewithout interrupting load/store instruction processing in the processor
core.
4.6 Loc k Mechanism
The 21264/EV68A doesnot c ontaina dedicated lock register, nor are system compo-
nents requiredto do so.
When a load-lock (LDx_L) instruction executes, datais accessed from the Dcache or
Bcache.If there is a cache miss, data is accessed from memory with a RdBlk command.
Its associatedcache line is f illedinto the D cache in the clean state, if it is not already
there.
When the store-conditional(STx_C) instruction executes, it is allowed to succeed if its
associatedcache line is still present in the Dcache and can be made writable; otherwise,
it fails.
This algorithmis successful because another agent in the system writing to the cache
line betweenthe load-lock and the store-conditional cache line would make the cache
line invalid.This mechanism’s coherence is based on the following four items:
1. LDx_L instructionsare processed in-order in relation to the associated STx_C.
2. Oncea blockis locked by way ofan LDx_Linstruction, no internal agent can evict
the blockfrom the Dcache as a side-effect of its processing.
3. Any externalagent that intends to update the contents of the stored block must use
an invalidatingprobe command to inform the 21264/EV68A.
4. The systemis the only agent with sufficient information to manage the tasks of fair-
nessand liveness. However, to enable these tasks, the 21264/EV68A only generates
externalcommands for nonspeculative STx_C instructions, and once given a suc-
cessindication from the system, must faithfully update the Dcache with the STx_C
value.
The systemis entirely responsible for item number three. The 21264/EV68A plays an
active rolein items one, two, and four.