Compaq EV68A Initialization and Configuration

21264/EV68A Hardware Reference Manual Initialization and Configuration 7–1
7
Initialization and Configuration
This chapterprovides information on 21264/EV68A-specific microprocessor system
initializationand configuration. It is organized as follows:
•Power-up reset flow
•Fault reset flow
•Energystar certification and sleep mode flow
•Warmre set flow
•Array initialization
•Initializationmode processing
•External interface initialization
•Internalprocessor register (IPR) reset state
•IEEE 1149.1test port reset
•Reset statemachine state transitions
•Phase-lockedloop (PLL) functional description
Initializationis controlled by the reset state machine,which is responsible for four
major operations.Table 7–1 describes the four major operations.
7.1 Power-Up Reset Flowand the Reset_L and DCOK_H Pins
The 21264/EV68Areset sequence is triggered using the two input signalsReset_L and
DCOK_H ina sequence that is described in Section 7.1.1. After Reset_L is deasserted,
the followingsequence of operations takes place:
Table 7–1 21264/E V68AR eset State Machine Major Operations
Operation Function
Rampup Sequencethe PLL input and output dividers (Xdiv and Zdiv) to gradually raisethe internal
GCLKfrequency and generate time intervals for the PLL to re-establishlock.
BiST/SROM Receive a synchronous transfer on the ClkFwdRst_H pin in order to start b uilt-in self-test and
SROM load at a predictable GC LKc ycle.
Clockforward
interface Receivea synchronous transfer on the ClkFwdRst_H pinin order to initialize the clock for- wardinginterface.
Rampdown Sequencethe PLL input and output dividers (Xdiv and Zdiv) to gradually lowerthe internal
GCLKfrequency during sleep mode.