Mbox IPRs

Table 5–17 DTB Alternate Processor Mode Register Fields Description (Continued)

Name

Extent

Type

Description

 

 

 

 

 

 

ALT_MODE[1:0]

[1:0]

WO

Alt_Mode:

 

 

 

 

ALT_MODE[1:0]

Mode

 

 

 

00

Kernel

 

 

 

01

Executive

 

 

 

10

Supervisor

 

 

 

11

User

 

 

 

 

 

5.3.4 Dstream TB Invalidate All Process (ASM=0) Register – DTB_IAP

The Dstream translation buffer invalidate all process (ASM=0) register (DTB_IAP) is a write-only pseudo register. Write transactions to this register invalidate all DTB entries in which the address space match (ASM) bit is clear.

5.3.5 Dstream TB Invalidate All Register – DTB_IA

The Dstream translation buffer invalidate all register (DTB_IA) is a write-only pseudo register. Write transactions to this register invalidate all DTB entries and reset the DTB not-last-used pointer to its initial state.

5.3.6 Dstream TB Invalidate Single Registers 0 and 1 – DTB_IS0,1

The Dstream translation buffer invalidate single registers (DTB_IS0 and DTB_IS1) are write-only pseudo registers through which software may invalidate a single entry in the DTB arrays. Writing a virtual page number to one of these registers invalidates any DTB entry in the corresponding memory pipeline which meets one of the following cri- teria:

The DTB entry’s virtual page number matches DTB_IS[47:13] and its ASN field matches DTB_ASN[63:56].

The DTB entry’s virtual page number matches DTB_IS[47:13] and its ASM bit is set.

Figure 5–29shows the Dstream translation buffer invalidate single registers.

Figure 5–29 Dstream Translation Buffer Invalidate Single Registers

63

48 47

13 12

0

 

 

 

 

 

 

VA[47:13]

LK99-0015A

21264/EV68A Hardware Reference Manual

Internal Processor Registers 5–27

Page 169
Image 169
Compaq EV68A Dstream TB Invalidate All Process ASM=0 Register Dtbiap, Dstream TB Invalidate All Register Dtbia, ALTMODE10