Compaq EV68A specifications Index-8

MB, 21264/EV68A command, 4–13 ,4–21

MB_CNT Cbox CSR, operation, 2–32MBDone, SysDc command, 4–13

Mbox

Dcache control register DC_CTL, 5–30Dcache status register DC_STAT, 5–31described, 2–12

Dstream translation buffer, 2–13

DTB address space number registers 0 and 1 DTB_ASNx, 5–28

DTB alternate processor mode register DTB_ALTMODE, 5–26

DTB invalidate-all (ASM=0) process register DTB_IAP, 5–27

DTB invalidate-all process register DTB_IA, 5–27

DTB invalidate-single registers 0 and 1 DTB_ISx, 5–27

DTB PTE array write registers 0 and 1 DTB_PTEx, 5–26

DTB tag array write registers 0 and 1

DTB_TAGx, 5–25internal processor registers, 5–2load queue, 2–13

Mbox control register M_CTL, 5–29memory management status register MM_STAT, 5–28

miss address file, 2–13order traps, 2–31

pipeline abort delay with order trap, 2–16pipeline abort delays, 2–16

store queue, 2–13MBOX_BC_PRB_STALL Cbox CSR, defined,

5–35

MCHK interrupt, 6–14

Mechanical specifications, 3–17

Memory

error case summary for, 8–11filling Dcache errors, 8–8filling Icache errors, 8–7

Memory address space

load instructions with, 2–27merging rules, 2–30

store instructions with, 2–28Memory barrier instructions

translation to external interface, 4–5Memory barriers, 2–32

Memory reference unit. See Mbox

MF_FPCR instruction, 6–12

Microarchitecture summarized, 2–1

MiscVref signal pin, 3–5

Miss address file, 2–13

I/O address space loads, 2–27memory address space loads, 2–27memory address space stores, 2–28

MM_STAT memory management status register, 5–28

at power-on reset state, 7–16MT_FPCR instruction, 6–12

MT_FPCR synchronous trap, 6–14

N

NoConnect pin type, 3–3

Nonexistent memory processing, 4–38

NOP, 21264/EV68A command, 4–21

Note convention, xxi

Numbering convention, xxi

NXM. See Nonexistent memory NZNOP, 21264/EV68A command, 4–21

O

O_OD pin type, 3–3 ,9–2values for, 9–4

O_OD_TP pin type, 3–3 ,9–2values for, 9–4

O_PP pin type, 3–3 ,9–2values for, 9–5

O_PP_CLK pin type, 3–3 ,9–2values for, 9–5

OPCDEC fault, 6–13

Opcodes

IEEE floating-point,A–9independent floating-point,A–11reserved for Compaq, A–8reserved for PALcode, A–9summary of, A–12

VAX floating-point,A–11Open-drain driver for test pins. See O_OD_TP

Open-drain output driver. See O_OD pin type

Operating temperature, 10–1

P

Packaging, 3–18

Paired instruction fetch order, 6–9

PAL_BASE register, 5–15

after fault reset, 7–8after warm reset, 7–11

at power-on reset state, 7–15through sleep mode, 7–10

Index–8 21264/EV68A Hardware Reference Manual