Compaq EV68A specifications 20Internal Processor Registers

Ibox IPRs

Table 5–12 Ibox Status Register Fields Description (Continued)

Name	Extent	Type	Description
TRAP	[37:34]	RO	ProfileMe Trap Types.
TYPE[3:0]			If the profiled instruction caused a trap (indicated by I_STAT[TRP]), this
			field indicates the trap type as listed here:
			Value	Trap Type
			0	Replay
			1	Invalid (unused)
			2	DTB Double miss (3 level page tables)
			3	DTB Double miss (4 level page tables)
			4	Floating point disabled
			5	Unaligned Load/Store
			6	DTB Single miss
			7	Dstream Fault
			8	OPCDEC
			9	Invalid (use PMPC, described below)
			10	Machine Check
			11	Invalid (use PMPC, described below)
			12	Arithmetic
			13	Invalid (use PMPC, described below)
			14	MT_FPCR
			15	Reset

Traps due to ITB miss, Istream access violation, or interrupts are not reported in the trap type field because they do not cause pipeline aborts. Instead, these traps cause pipeline redirection and can be distinguished by examining the PMPC value for the presence of the corresponding PAL- code entry offset addresses indicated below. In these cases, the ProfileMe interrupt will normally be delivered when exiting the trap PALcode flow and the EXC_ADDR register will contain the original PC that encoun- tered the redirect trap.

PMPC[14:0] Trap

0581	ITB miss
0481	Istream Access Violation
0681	Interrupt

ICM	[33]	RO	ProfileMe Icache Miss.
			This bit indicates that the profiled instruction was contained in an aligned
			4-instruction Icache fetch block that requested a new Icache fill stream.
OVR[2:0]	[32:30]	RO	ProfileMe Counter 0 Overcount.
			This bit indicates a value (0-7) that must be subtracted from the counter 0
			result to obtain an accurate count of the number of instructions retired in
			the interval beginning three cycles after the profiled instruction reaches
			pipeline stage 2 and ending four cycles after the profiled instruction is
			retired.
PAR	[29]	W1C	Icache Parity Error.
			This bit indicates that the Icache encountered a parity error on instruction
			fetch. When a parity error is detected, the Icache is flushed, a replay trap
			back to the address of the error instruction is generated, and a correctable
			read interrupt is requested. See also I_STAT[LAM].
LAM	[28]	RO	When set, indicates that an error in the line predictor set I_STAT[PAR].
			I_STAT[LAM] is set only when I_STAT[PAR] is set; is subsequently
			cleared when I_STAT[PAR] is cleared (when a 1 is written to
			I_STAT[PAR] ).
Reserved	[28:0]	RO	Reserved for COMPAQ.

5–20Internal Processor Registers 21264/EV68A Hardware Reference Manual