Compaq EV68A specifications Guideline 29 JSR, JMP, RET, and Jsrcor in PALcode

Restriction 27: Reset of ‘Force-Fail Lock Flag’ State in PALcode

D.23 Restriction 27: Reset of ‘Force-Fail Lock Flag’ State in PALcode

A virtual mode load or store is required in PALcode before the execution of any load- locked or store-conditional instructions. The virtual-mode load or store may not be a HW_LD, HW_ST, LDx_L, ECB, or WH64.

D.24 Restriction 28: Enforce Ordering Between IPRs Implicitly Writ- ten by Loads and Subsequent Loads

Certain IPRs, which are updated as a result of faulting memory operations, require soft- ware assistance to maintain ordering against newer instructions. Consider the following code sequence:

HW_MFPR IPR_MM_STAT

LDQ rx, (ry)

These instructions would typically be issued in-order. The HW_MFPR is data-ready and both instructions use a lower subcluster. However, the HW_MFPRs (and HW_MTPRs) respond to certain resource-busy indications and are not issued when the Mbox informs the Ibox that a certain set of resources (store-bubbles) are busy. The LDs respond to a different set of resource-busy indications (load-bubbles) and could be issued around the HW_MFPR in the presence of the former. Software assistance is required to enforce the issue order. One sure way to enforce the issue order is to insert an MB instruction before the first load that occurs after the HW_MFPR MM_STAT. The VA, VA_FORM, and DC_CTL registers require a similar constraint. All LOAD instructions except HW_LD might modify any or all of these registers. HW_LD does not modify MM_STAT.

D.25 Guideline 29 : JSR, JMP, RET, and JSR_COR in PALcode

Unprivileged JSR, JMP, RET, and JSR_COR instructions will always mispredict when used in PALcode. In addition, HW_RET to a PALmode target will always mispredict since the JSR stack only predicts native-mode return addresses. HW_RET to a native- mode target uses the JSR stack for prediction and should usually be used when exiting PALmode in order to maintain JSR stack alignment since all PALmode traps also push the value of the EXC_ADDR on the JSR stack.

Privileged versions of the JSR type instructions (HW_JSR,HW_JMP,HW_JSR_COR) can be used both within PALmode or to exit PALmode and generate a predicted target based on their hint bits and the current processor PALmode state.

D.26 Restriction 30 : HW_MTPR and HW_MFPR to the Cbox CSR

External bus activity must be isolated from writes and reads to the Cbox CSR. This requires that all Dstream and Istream fills must be avoided until after the HW_MTPR/ HW_MFPR updates are completed. An MB instruction can block Dstream activity, but blocking all Istream fills, including prefetches, requires more extensive code. The fol- lowing code example blocks all Istream fill requests and stalls instruction fetch until after the desired MTPR/MFPR action is completed. This code disables Istream prefetching by way of a HW_MTPR to I_CTL[SBE], IC_FLUSH, and HW_RET_STALL sequence.

21264/EV68A Hardware Reference Manual PALcode Restrictions and Guidelines D–15