Compaq EV68A specifications 10Privileged Architecture Library Code

Internal Processor Register Access Mechanisms

Table 6–7 Paired Instruction Fetch Order (Continued)

Second
Instruction		First Instruction
Explicit	Reader reads	Write-one-to-clear	Reader reads second	Scoreboard bits stall second
Writer	second register.	bits, or performance	register. Writer cannot	writer in map stage until first
	Writer cannot	counter special case.	write second register	writer is retired.
	write second	For example, perfor-	until it is retired.
	register until it	mance counter incre-
	is retired.	ments are typically
		not scoreboarded
		against read transac-
		tions.

For convenience of implementation, there is no IPR scoreboard bit checking within the same fetch block (octaword-aligned octaword).

•Within one fetch block, there can be only one explicit writer (HW_MTPR) to an IPR in a particular scoreboard group.

•Within one fetch block, an explicit writer (HW_MTPR) to an IPR in a particular scoreboard group cannot be followed by an explicit reader (HW_MFPR) to an IPR in that same scoreboard group.

•Within one fetch block, an explicit writer (HW_MTPR) to an IPR in a particular scoreboard group cannot be followed by an implicit reader to an IPR in that score- board group. This case covers writes to DTB_PTE or DTB_TAG followed by a LD, ST, or any memory operation, including HW_RETs without the ‘stall’ bit set.

6.5.5Correct Ordering of Explicit Writers Followed by Implicit Readers

Across fetch blocks, the correct ordering of the explicit write of the DTB_PTE or DTB_TAG followed by an implicit reader (memory operation) is guaranteed using the IPR scoreboard bits.

However, there are cases where correct ordering of explicit writers followed by implicit readers cannot be guaranteed using the IPR scoreboard mechanism. If the instruction that implicitly reads the IPR does so before the issue stage of the pipeline, the score- board mechanism is not sufficient.

For example, modification of the ITB affects instructions before the issue state of the pipeline. In this case, PALcode must contain a HW_RET instruction, with its stall bit set, before any instruction that implicitly reads the IPR(s) in question. This prevents instructions that are newer than the HW_RET instruction from being successfully fetched, issued, and retired until after the HW_RET instruction is retired (or aborted).

There are also cases when the HW_RET with the STALL bit mechanism is not suffi- cient. There may be additional propagation delay past the retirement of the HW_RET instruction. In these cases, instead of using a HW_RET, a suggested method of ensur- ing the ordering is coding a group of 5 fetch blocks, where the first contains the HW_MTPR to the IPR, the second contains a HW_MTPR to the same IPR or one in the same scoreboard group, and where the following 3 fetch blocks each contain at least one non-NOP instruction. See Appendix D for a listing of cases where this method is recommended.

6–10Privileged Architecture Library Code 21264/EV68A Hardware Reference Manual