Compaq EV68A specifications Dcache Data Single-Bit Correctable ECC Error, Load Instruction

Dcache Data Single-Bit Correctable ECC Error

3.The virtual address associated with the error is available in the VA register.

4.The PALcode flushes the error block by temporarily disabling

DC_CTL[DCTAG_PAR_EN] and evicting the block using two HW_LD instruc- tions. The onchip duplicate tag provides the correct victim address and cache coherence state.

If a retried load instruction detects the Dcache tag parity error, the memory reference may have already been retired, so the EXC_ADDR is not available. In this case, the error is uncorrectable and the Mbox performs the following actions:

•Either DC_STAT[TPERR_P0] or DC_STAT[TPERR_P1] is set, indicating the source of the error.

•When enabled, a machine check (MCHK) is posted. The MCHK is taken when not in PALmode.

8.4Dcache Data Single-Bit Correctable ECC Error

The following operations may cause Dcache data ECC errors:

•Load instructions

•Stores of less than quadword length

•Dcache victim read transactions

The hardware flow used for Dcache data ECC errors depends on the event that caused the error.

8.4.1 Load Instruction

Loads that read data from the Dcache may do so either in the same cycle as the Dcache tag probe (typical case) or in some subsequent cycle (load-queue retry). The hardware functional flows for these two error cases differ slightly.

When a load instruction reads the Dcache data array in the same cycle as the tag array, if an ECC error occurs on the LSD ECC error detectors, then the Ibox stops retiring instructions and does not resume retiring until after hardware recovers from the error.

If an ECC error occurs on the LSD ECC error detectors, when a load instruction reads the Dcache tag array before it reads the Dcache data array, then the load instruction may have already been retired. In either case:

•The incorrect data is written into the load instruction’s destination register; however, the load queue retains the state associated with the load instruction.

•A consumer of the load instruction’s data may be issued before the error is recognized; however, the Ibox will invoke a replay trap at an instruction that is older than (or equal to) any instruction that consumes the load instruction’s data, and then stalls the replayed Istream in the map stage of the pipeline until the error is corrected.

•Given a READ_ERR read-type from the Mbox for the error load instruction, the Cbox scrubs the block in the Dcache by evicting the block into the victim buffer (thereby scrubbing it) and writing it back into the Dcache as follows:

– C_STAT[DSTREAM_DC_ERR] is set.

21264/EV68A Hardware Reference Manual Error Detection and Error Handling 8–3