Compaq EV68A Translation Buffer TB Fill Flows, DTB Fill, 14Privileged Architecture Library Code

Translation Buffer (TB) Fill Flows

Table 6–8 PALcode Exception Entry Locations (Continued)

Entry Name	Type	Offset16	Description
MCHK	Interrupt	500	Machine check.
ITB_MISS	Fault	580	Istream TB miss.
ARITH	Synch. Trap	600	Arithmetic exception or update to FPCR.
INTERRUPT	Interrupt	680	Interrupts: hardware, software, and AST.
MT_FPCR	Synch. Trap	700	Invoked when a MT_FPCR instruction is issued.
RESET/WAKEUP	Interrupt	780	Chip reset or wake-up from sleep mode.

6.9 Translation Buffer (TB) Fill Flows

This section shows the expected PALcode flows for DTB miss and ITB miss. Familiar- ity with 21264/EV68A IPRs is assumed.

6.9.1 DTB Fill

Figure 6–5shows single-miss DTB instructions flow.

Figure 6–5 Single-Miss DTB Instructions Flow Example

hw_mfprp23, EV6__EXC_ADDR hw_mfprp4, EV6__VA_FORM hw_mfprp5, EV6__MM_STAT hw_mfpr p7, EV6__EXC_SUM

hw_mfpr p6, EV6__VA bic p7, #1, p7

xor p4, p6, p4 xor p4, p6, p4

trap__dtbm_single_vpte: hw_ldq/v p4, (p4)

blt p_misc, trap__d1to1 blbcp4, trap__invalid_dpte

and p4, #^x80, p7 xor p7, #^x80, p7

;(0L) get exception address

;(4-7,1L) get vpte address

;(0L) get miss info

;(0L) get exc_sum for ra

;(4-7,1L) get original va

;clear double miss flag

;interlock p4 and p6

;restore p4

;(1L) get vpte

;(xU) <63>=1 => 1-to-1

;(xU) invalid => branch

;isolate mb bit

;flip mb bit

ALIGN_FETCH_BLOCK <^x47FF041F>
PVC_VIOLATE <2>	; ignore scoreboard violation
hw_mtprp6, EV6__DTB_TAG0	; (2&6,0L) write tag0
hw_mtpr p6, EV6__DTB_TAG1	; (1&5,1L) write tag1
hw_mtprp4, <EV6__DTB_PTE0 ! ^x44>	; (0,4,2,6)	(0L)	write pte0
hw_mtprp4, <EV6__DTB_PTE1 ! ^x22>	; (3,7,1,5)	(1L)	write pte1

6–14Privileged Architecture Library Code 21264/EV68A Hardware Reference Manual