Compaq EV68A specifications 12 I/O Write Buffer and the WMB Instruction, Other Mbox Replay Traps

I/O Write Buffer and the WMB Instruction

The Ibox contains extra hardware to reduce the frequency of the store-loadtrap. There is a 1-bit by 1024-entry VPC-indexed table in the Ibox called the stWait table. When an Icache instruction is fetched, the associated stWait table entry is fetched along with the Icache instruction. The stWait table produces 1 bit for each instruction accessed from the Icache. When a load instruction gets a store-loadorder replay trap, its associated bit in the stWait table is set during the cycle that the load is refetched. Hence, the trapping load instruction’s stWait bit will be set the next time it is fetched.

The IQ will not issue load instructions whose stWait bit is set while there are older unis- sued store instructions in the queue. A load instruction whose stWait bit is set can be issued the cycle immediately after the last older store instruction is issued from the queue. All the bits in the stWait table are unconditionally cleared every 16384 cycles, or every 65536 cycles if I_CTL[ST_WAIT_64K] is set.

2.11.2 Other Mbox Replay Traps

The Mbox also uses replay traps to control the flow of the load queue and store queue, and to ensure that there are never multiple outstanding misses to different physical addresses that map to the same Dcache or Bcache line. Unlike the order traps, however, these replay traps are invoked on the incoming instruction that triggered the condition.

2.12 I/O Write Buffer and the WMB Instruction

The I/O write buffer (IOWB) consists of four 64-byte entries with the associated address and control logic used to buffer I/O write data between the store queue (SQ) and the system port.

2.12.1 Memory Barrier (MB/WMB/TB Fill Flow)

The Cbox CSR SYSBUS_MB_ENABLE bit determines if MB instructions produce external system port transactions. When the SYSBUS_MB_ENABLE bit equals 0, the Cbox CSR MB_CNT[3:0] field contains the number of pending uncommitted transac- tions. The counter will increment for each of the following commands:

•RdBlk, RdBlkMod, RdBlkI

•RdBlkSpec (valid), RdBlkModSpec (valid), RdBlkSpecI (valid)

•RdBlkVic, RdBlkModVic, RdBlkVicI

•CleanToDirty, SharedToDirty, STChangeToDirty, InvalToDirty

•FetchBlk, FetchBlkSpec (valid), Evict

•RdByte, RdLw, RdQw, WrByte, WrLW, WrQW

The counter is decremented with the C (commit) bit in the Probe and SysDc commands (see Section 4.7.7). Systems can assert the C bit in the SysDc fill response to the com- mands that originally incremented the counter, or attached to the last probe seen by that command when it reached the system serialization point. If the number of uncommitted transactions reaches 15 (saturating the counter), the Cbox will stall MAF and IOWB processing until at least one of the pending transactions has been committed. Probe pro- cessing is not interrupted by the state of this counter.

2–32Internal Architecture 21264/EV68A Hardware Reference Manual