Compaq EV68A 30defines the interleaved scheme for the wrap order, System Wrap and Deliver Data

System Port

point is the QW pointed to by the 21264/EV68A; however, some systems may find it more beneficial to begin the transfer elsewhere. The system must always indicate the starting point to the 21264/EV68A. The wrap order for subsequent QWs is interleaved.

Table 4–29defines the method for systems to specify wrap and deliver data.

Table 4–29 System Wrap and Deliver Data

Source/
Destination	SysDc[4:2]		SysDc[1:0]	Size	Rules
Memory	100	(ReadData)	SysAddOut_L[5:4]	Block (64 Bytes)	See Note 1
Memory	101(ReadDataDirty)		SysAddOut_L[5:4]	Block (64 Bytes)	See Note 1
Memory	110 (ReadDataShared)		SysAddOut_L[5:4]	Block (64 Bytes)	See Note 1
Memory	111(Read DataShared/Dirty)		SysAddOut_L[5:4]	Block (64 Bytes)	See Note 1
Memory	010	(WriteData)	SysAddOut_L[5:4]	Block (64 Bytes)	See Note 1
I/O	100	(ReadData)	SysAddOut_L[5:4]	QW (8-64 Bytes)	See Note 1
I/O	100	(ReadData)	SysAddOut_L[4:3]	LW(4-32 Bytes)	See Note 2
I/O	100	(ReadData)	SysAddOut_L[4:3]	Byte/Word	See Note 2
I/O	010	(WriteData)	SysAddOut_L[5:4]	QW (8-64 Bytes)	See Note 1
I/O	010	(WriteData)	SysAddOut_L[5:4]	LW(4-32 Bytes)	See Note 1
I/O	010	(WriteData)	SysAddOut_L[5:4]	Byte/Word	See Note 1

Note 1: Transfers to and from the 21264/EV68A have eight data cycles for a total of eight quadwords. The starting point is defined by the system. The pre- ferred starting point is the one pointed to by SysAddOut_L[5:4]. Systems can insert the SysAddOut_L[5:4] into the SysDc[1:0] field of the com- mand. See Table 4–30for the wrap order.

Note 2: LW and byte/word read transfers differ from all other transfers. The system unloads only four QWs of data into eight data cycles by sending each QW twice (referred to as double-pumped data transfer). The first QW returned is determined by SysAddOut_L[4:3]. The system again may elect to choose its own starting point for the transfer and insert that value into SysDc[1:0]. See Table 4–31for the wrap order.

Table 4–30defines the interleaved scheme for the wrap order.

Table 4–30 Wrap Interleave Order

PA Bits [5:3] of Transferred QW

First quadword	000	010	100	110
Second quadword	001	011	101	111
Third quadword	010	000	110	100
Fourth quadword	011	001	111	101
Fifth quadword	100	110	000	010

21264/EV68A Hardware Reference Manual Cache and External Interfaces 4–37