Compaq EV68A specifications Index-11

Store instructions

Dcache ECC errors with, 8–4I/O address space, 2–29

I/O reference ordering, 2–31Mbox order traps, 2–31memory address space, 2–28memory reference ordering, 2–30translation to external interface, 4–5

Store queue, 2–13Store-load order trap, 2–31

STx_C instructions

in-order processing for, 4–15locking mechanism for, 4–14

SUM bit. See Summary bit Summary bit, in FPCR, 2–36

Supply voltage signal pins. See I_DC_POWER pin type

Synchronous static random-access memory. See SSRAMs

SYS_BPHASE_LD_VECTOR Cbox CSR, 4–18defined, 5–38

SYS_BUS_FORMAT Cbox CSR, defined, 5–34

SYS_BUS_SIZE Cbox CSR, 4–21defined, 5–34

SYS_CLK_DELAY Cbox CSR, defined, 5–36

SYS_CLK_LD_VECTOR Cbox CSR, 4–18defined, 5–38

SYS_CLK_RATIO Cbox CSR, defined, 5–34

SYS_CLKFWD_ENABLE Cbox CSR, defined, 5–36

SYS_CPU_CLK_DELAY Cbox CSR

defined, 5–38

SYS_DDM_FALL_EN Cbox CSR, 4–18

defined, 5–36

SYS_DDM_RD_FALL_EN Cbox CSR, 4–18

SYS_DDM_RD_RISE_EN Cbox CSR, 4–19

SYS_DDM_RISE_EN Cbox CSR, 4–18defined, 5–36

SYS_DDMF_ENABLE Cbox CSR, 4–19defined, 5–36

SYS_DDMR_ENABLE Cbox CSR, 4–19defined, 5–36

SYS_FDBK_EN Cbox CSR, 4–18defined, 5–38

SYS_FRAME_LD_VECTOR Cbox CSR, 4–19 ,4–31

defined, 5–38SYS_RCV_MUX_CNT_PRESET Cbox CSR, 4–31

defined, 5–36SYS_RCV_MUX_PRESET Cbox CSR, 4–33SysAddIn_L signal pins, 3–5

SysAddInClk_L signal pin, 3–5

SysAddOut_L signal pins, 3–5

SysAddOutClk_L signal pin, 3–5

SYSBUS_ACK_LIMIT Cbox CSR, 4–25defined, 5–34

SYSBUS_FORMAT Cbox CSR, 4–21

SYSBUS_MB_ENABLE Cbox CSR, 4–23

defined, 5–34operation, 2–32

SYSBUS_VIC_LIMIT Cbox CSR, 4–26defined, 5–34

SysCheck_L signal pin, 3–5SYSCLK, 4–31

SysData_L signal pin, 3–5

SysDataInClk_H signal pin, 3–5

SysDataInValid_L signal pin, 3–5rules for, 4–34

SysDataOutClk_L signal pin, 3–5

SysDataOutValid_L signal pin, 3–5rules for, 4–35

SysDc commands, 4–11system probes, with, 4–42

SysDc field, system to 21264/EV68A commands, 4–29

SYSDC_DELAY Cbox CSR, 4–32defined, 5–38

SysFillValid_L signal pin, 3–5rules for, 4–35

System clock ratio configuration, 7–4System initialization, 7–7

System interface clocks, programming, 4–18System port, 4–16

SysVref signal pin, 3–6

T

Tag parity errors, 8–2

TB fill flow, 2–34 ,6–14

Tck_H signal pin, 3–6

Tdi_H signal pin, 3–6

Tdo_H signal pin, 3–6

Temperatures

maximium average per frequency, 10–2operating, 10–1

Terminology, xix

TestStat_H signal pin, 3–6

purpose for, 11–4

with BiST and SROM load, 7–6

21264/EV68A Hardware Reference Manual Index–11