Compaq EV68A specifications Typical Uniprocessor Configuration

Design Examples

Figure 2–12 Typical Uniprocessor Configuration

L2 Cache	21264		21272 Core	Duplicate
			Logic Chipset	Tag Store
Tag		Tag		(Optional)
Store
		Address	Control
		Out	Chips
		Address		DRAM
		Address	Data Slice
				Arrays
		In	Chips
Data
		Data
Store			Host PCI	Address
		Data
			Bridge Chip	Data

64-bit PCI Bus

FM-05573-EV67

Figure 2–13shows a typical multiprocessor system, each processor with a second-level cache. Each interface controller must employ a duplicate tag store to maintain cache coherency. This system configuration could be used in a networked database server application.

Figure 2–13 Typical Multiprocessor Configuration

21272 Core

21264DRAM Logic Chipset

Arrays

L2			Address
Cache
	Control		Data
		Chip
21264
	Data Slice
			DRAM
		Chips
			Arrays
L2
Cache	Host PCI	Host PCI	Address
	Bridge Chip	Bridge Chip	Data

64-bit PCI Bus

64-bit PCI Bus

FM-05574-EV67

21264/EV68A Hardware Reference Manual Internal Architecture 2–39