Compaq EV68A specifications Internal Processor Register Access Mechanisms

Internal Processor Register Access Mechanisms

Table 6–6describes the HW_MFPR and HW_MTPR instructions fields.

Table 6–6 HW_MFPR and HW_MTPR Instructions Fields Descriptions

Extent	Mnemonic	Value	Description
[31:26]	OPCODE	1916	The opcode value for the HW_MFPR instruction.
		1D16	The opcode value for the HW_MTPR instruction.
[25:21]	RA	—	Destination register for the HW_MFPR instruction. It should be R31
			for the HW_MTPR instruction.
[20:16]	RB	—	Source register for the HW_MTPR instruction. It should be R31 for the
			HW_MFPR instruction.
[15:8]	INDEX	—	IPR index.
[7:0]	SCBD_MASK	—	Specifies which IPR scoreboard bits in the IQ are to be applied to this
			instruction. If a mask bit is set, it indicates that the corresponding IPR
			scoreboard bit should be applied to this instruction.

6.5 Internal Processor Register Access Mechanisms

This section describes the hardware and software access mechanisms that are used for the 21264s IPRs.

Because the Ibox reorders and executes instructions speculatively, extra hardware is required to provide software with the correct view of the architecturally-defined state. The Alpha architecture defines two classes of state: general-purpose registers and memory. Register renaming is used to provide architecturally-correct register file behavior. The Ibox and Mbox each have dedicated hardware that provides correct mem- ory behavior to the programmer. Because the internal processor registers are implemen- tation-specific, and their state is not defined by the Alpha architecture, access mechanisms for these registers may be defined that impose restrictions and limitations on the software that uses them.

For every IPR, each instruction type can be classified by how it affects and is affected by the value held by that IPR.

•Explicit readers are HW_MFPR instructions that explicitly read the value of the IPR.

•Implicit readers are instructions whose behavior is affected by the value of the IPR. For example, each load instruction is an implicit reader of the DTB.

•Explicit writers are HW_MTPR instructions that explicitly write a value into the IPR.

•Implicit writers are instructions that may write a value into the IPR as a side effect of execution. For example, a load instruction that generates an access violation is an implicit writer of the VA, MM_STAT, and EXC_ADDR IPRs. In the 21264/ EV68A, only instructions that generate an exception will act as implicit IPR writ- ers.

Only certain IPRs, such as those with write-one-to-clear bits, are both implicitly and explicitly written. The read-write semantics of these IPRs is controlled by software.

21264/EV68A Hardware Reference Manual Privileged Architecture Library Code 6–7