Compaq EV68A Table A-11 Exceptional Input and Output Conditions, Alpha Instruction Set A-15

IEEE Floating-Point Conformance

If one of these bits is set, and an instruction with the /S qualifier set generates the associated exception, the 21264/EV68A produces the IEEE nontrapping result and suppresses the trap. These nontrapping responses include correctly signed infinity, largest finite number, and Quiet NaNs as specified by the IEEE standard.

The 21264/EV68A does not produce a denormal result for the underflow exception. Instead, a true zero (+0) is written to the destination register. In the 21264/EV68A, the FPCR underflow to zero (UNDZ) bit must be set if the underflow disable (UNFD) bit is set. If desired, trapping on underflow can be enabled by the instruc- tion and the FPCR, and software may compute the denormal value as defined in the IEEE standard.

The 21264/EV68A records floating-point exception information in two places:

•The FPCR status bits record the occurrence of all exceptions that are detected, whether or not the corresponding trap is enabled. The status bits are cleared only through an explicit clear command (MT_FPCR); hence, the exception information they record is a summary of all exceptions that have occurred since the last time they were cleared.

•If an exception is detected and the corresponding trap is enabled by the instruction, and is not disabled by the FPCR control bits, the 21264/EV68A will record the condition in the EXC_SUM register and initiate an arithmetic trap.

The following items apply to Table A–11:

•The 21264/EV68A traps on a denormal input operand for all arithmetic operations unless FPCR[DNZ] = 1.

•Input operand traps take precedence over arithmetic result traps.

•The following abbreviations are used: Inf: Infinity

QNaN: Quiet NaN

SNaN: Signalling NaN

CQNaN: Canonical Quiet NaN

For IEEE instructions with /S, Table A–11lists all exceptional input and output conditions recognized by the 21264/EV68A, along with the result and exception generated for each condition.

Table A–11 Exceptional Input and Output Conditions

	21264/EV68A Hardware
Alpha Instructions	Supplied Result	Exception
ADDx SUBx INPUT
Inf operand	±Inf	(none)
QNaN operand	QNaN	(none)
SNaN operand	QNaN	Invalid Op
Effective subtract of two Inf operands	CQNaN	Invalid Op
ADDx SUBx OUTPUT

21264/EV68A Hardware Reference Manual Alpha Instruction Set A–15