Compaq EV68A specifications Cbox Writemany Chain Order

Cbox CSRs and IPRs

•The order of multibit vectors is [MSB:LSB], so the LSB is first bit in the Cbox chain.

Table 5–25describes the Cbox WRITE_MANY chain order from LSB to MSB.

Table 5–25 Cbox WRITE_MANY Chain Order

Cbox WRITE_MANY Chain	Description	For Information:
BC_VALID_MODE	Control Bcache block parity calculation	Section 8.8
INIT_MODE[0]	Enable initialize mode	Section 7.6
BC_SIZE[3:0]	Bcache size	Table 4–42
BC_ENABLE[0]	Enable the Bcache	Table 4–42
BC_ENABLE	Duplicate CSR	Table 4–42
BC_SIZE[0:3]	Duplicate CSR	Table 4–42
BC_ENABLE1	Duplicate CSR	Table 4–42
BC_ENABLE1	Duplicate CSR	Table 4–42
BC_ENABLE1	Duplicate CSR	Table 4–42
INVAL_TO_DIRTY_ENABLE[1]	WH64 acknowledges	Table 4–15
ENABLE_EVICT	Enable issue evict	Table 4–1
BC_ENABLE	Duplicate CSR	Table 4–42
INVAL_TO_DIRTY_ENABLE[0]	WH64 acknowledges	Table 4–15
BC_ENABLE	Duplicate CSR	Table 4–42
BC_ENABLE	Duplicate CSR	Table 4–42
BC_ENABLE	Duplicate CSR	Table 4–42
SET_DIRTY_ENABLE[0]	SetDirty acknowledge programming	Table 4–16
INVAL_TO_DIRTY_ENABLE[0]	Duplicate CSR	Table 4–15
SET_DIRTY_ENABLE[2:1]	SetDirty acknowledge programming	Table 4–16
BC_BANK_ENABLE[0]	Enable bank mode for Bcache	Section 4.8.5
BC_SIZE[0:3]	Duplicate CSR	Table 4–42
INIT_MODE	Duplicate CSR	Section 7.6
BC_WRT_STS[0:3]	Write status for Bcache in initialize-mode	Section 7.6
	(Valid, Dirty, Shared, Parity)

1MBZ during initialization mode; see Section 7.6 for information.

Figure 5–37shows an example of PALcode used to write to the WRITE_MANY chain.

Figure 5–37 WRITE_MANY Chain Write Transaction Example

;

;Initialize the Bcache configuration in the Cbox

;BC_VALID_MODE = 1

;BC_ENABLE = 1

21264/EV68A Hardware Reference Manual Internal Processor Registers 5–39