Compaq EV68A specifications Data Wrapping Rules, 36Cache and External Interfaces

System Port

Figure 4–6 SysFillValid_L Timing

SysAddIn_L[14:0]	SysDc
	Transport Delay on Address
Command Receiver	T3
SysFillValid_L
SysData_L[63:0]	D0	D1	D2	D3	D4

FM-05823B.FH8

4.7.8.6 Data Wrapping

All data movement between the 21264/EV68A and the system is composed of 64 bytes in eight cycles on the data bus. All 64 bytes of memory data are valid. This applies to memory read transactions, memory write transactions, and system probe read transac- tions. The wrap order is interleaved. The internal data bus, which delivers data to the functional units and the Dcache, is 16 bytes wide, and so, no transfers happen until two data cycles occur on the interface.

Table 4–28lists the rules for data wrapping. I/O read and write addresses on the SysAddOut bus point to the desired byte, word, LW, or QW, with a combination of SysAddOut_L[5:3] and the mask field [7:0].

Table 4–28 Data Wrapping Rules

	Significant Address	Mask
Command	Bits	Type	Rules
ReadQW and	SysAddOut_L[5:3]	QW	SysAddOut_L[5:3] contains the exact PA bits of the first
WrQW			LDQ or STQ to the block. The mask bits point to the valid
			QWs merged in ascending order.
ReadLW and	SysAddOut_L[5:3]	LW	SysAddOut_L[5:3] contain the exact PA bits of the first
WrLW			LDL or STL to the block. The mask bits point to the valid
			LWs merged in ascending order within one hexword.
LDByte/Word	SysAddOut_L[5:3]	Byte	SysAddOut_L[5:3] contain the exact QW PA bits of the
and			LDByte/Word or STByte/Word instruction. The mask bits
STByte/Word			point to the valid byte in the QW.

The order in which data is provided to the 21264/EV68A (for a memory or I/O fill) or moved from the 21264/EV68A (write victims or probe reads) can be determined by the system. The system chooses to reflect back the same low-order address bits and the cor- responding octaword found in the SysAddOut field or the system chooses any other starting point within the block.

SysDc commands for the ReadData, ReadDataShared, and WriteData groups require that systems define the position of the first QW by inserting the appropriate value of SysAddOut_L[5:3] into bits [1:0] of the command field. The recommended starting

4–36Cache and External Interfaces 21264/EV68A Hardware Reference Manual