Compaq Computer Corporation Shrewsbury, Massachusetts
Revision/Update Information
21264/EV68A Hardware Reference Manual
Table of Contents
Cache and External Interfaces
Hardware Interface
Internal Processor Registers
Privileged Architecture Library Code
Mffpcr Mtfpcr
Initialization and Configuration
Testability and Diagnostics
Error Detection and Error Handling
Electrical Data
Thermal Management
21264/EV68A Boundary-Scan Register
Alpha Instruction Set
Glossary Index
21264/EV68A-to-Bcache Pin Interface
Figures
10-2 Type 2 Heat Sink
Tables
Xiv
VDD Idcpower
Page
Preface
Content
Audience
Documentation Included by Reference
For example
Terminology and Conventions
Abbreviations
W1S
W1C
Addresses
Aligned and Unaligned
Data Units
Signal Names
Do Not Care
External
Undefined
Do not care. a capital X represents any valid value
Page
Architecture
Introduction
Introduction
Addressing
Architecture
Integer Data Types
Floating-Point Data Types
21264/EV68A Microprocessor Features
21264/EV68A Microprocessor Features
21264/EV68A Microprocessor Features
21264/EV68A Microarchitecture
Internal Architecture
Internal Architecture
21264/EV68A Microarchitecture
Instruction Fetch, Issue, and Retire Unit
Virtual Program Counter Logic
Branch Predictor
21264/EV68A Block Diagram
Global Predictor
Local Predictor
Instruction-Stream Translation Buffer
Choice Predictor
Instruction Fetch Logic
Integer Issue Queue
Register Rename Maps
Hwret
Floating-Point Issue Queue
Exception and Interrupt Logic
Integer Execution Unit
Retire Logic
Integer Execution Unit-Clusters 0
PERR, MINxxx, MAXxxx, UNPKxx, PKxx
10Internal Architecture
Floating-Point Execution Unit
Onchip Caches
External Cache and System Interface Unit
21264/EV68A contains two onchip primary-level caches
Data Cache
Memory Reference Unit
12Internal Architecture
Pipeline Organization
Pipeline Organization
Srom Interface
Miss address file MAF Dstream translation buffer DTB
Stage 1 Instruction Slot
Stage 0 Instruction Fetch
14Internal Architecture
Stage 2 Map
Stage 3 Issue
Instruction Issue Rules
Instruction Issue Rules
Pipeline Aborts
Ebox and Fbox pipelines begin execution
Instruction Name, Pipeline, and Types
Instruction Group Definitions
FTOIS, Ftoit
Ebox Slotting
ITOFS, ITOFF, Itoft
Instruction Group Definitions and Pipeline Unit
U U L E L U E E L L E U
Instruction Class Latency in Cycles
Instruction Latencies
Hwmfpr
20Internal Architecture
Instruction Retire Rules
Instruction Retire Rules
Minimum Retire Latencies for Instruction Classes
Retire of Operate Instructions into R31/F31
Retire of Operate Instructions into R31/F31
Floating-Point Divide/Square Root Early Retire
BSR/JSR
Load Instructions to R31 and F31
Load Instructions to R31 and F31
Prefetch with Modify Intent LDS Instruction
Instructions Retired Without Execution
Special Cases of Alpha Instruction Execution
Special Cases of Alpha Instruction Execution
Prefetch, Evict Next LDQ and Hwldq Instructions
Load Hit Speculation
10 Pipeline Timing for Floating-Point Load Instructions
Cmov Instruction
Floating-Point Store Instructions
26Internal Architecture
Memory and I/O Address Space Instructions
Memory and I/O Address Space Instructions
Memory Address Space Load Instructions
2 I/O Address Space Load Instructions
Rules for I/O Address Space Load Instruction Data Merging
Memory Address Space Store Instructions
28Internal Architecture
Rules for I/O Address Space Store Instruction Data Merging
4 I/O Address Space Store Instructions
Instruction Ordering
MAF Memory Address Space Merging Rules
MAF Memory Address Space Merging Rules
Replay Traps
Replay Traps
Mbox Order Traps
Write Buffer and the WMB Instruction
12 I/O Write Buffer and the WMB Instruction
Other Mbox Replay Traps
Memory Barrier MB/WMB/TB Fill Flow
WMB Instruction Processing
MB Instruction Processing
12 TB Fill Flow Example Sequence
TB Fill Flow
13 TB Fill Flow Example Sequence
34Internal Architecture
Floating-Point Control Register
Performance Measurement Support-Performance Counters
Performance Measurement Support-Performance Counters
Floating-point control register Fpcr is shown in Figure
14 Floating-Point Control Register Fields
Floating-Point Control Register
36Internal Architecture
Amask and Implver Instruction Values
Amask and Implver Instruction Values
Design Examples
Design Examples
Amask
Implver
12 Typical Uniprocessor Configuration
Page
Hardware Interface
21264/EV68A Microprocessor Logic Symbol
Hardware Interface
21264/EV68A Microprocessor Logic Symbol
21264/EV68A Microprocessor Logic Symbol
21264/EV68A Signal Names and Functions
21264/EV68A Signal Names and Functions
Signal Pin Types Definitions
21264/EV68A Signal Descriptions
Dcokh
Pllvdd
TestStatH
21264/EV68A Signal Descriptions by Function
SysVref Domain SysAddInL140
Pin Assignments
Pin List Sorted by Signal Name
Pin Assignments
AC1
Pllvdd
10Hardware Interface
AA5
12Hardware Interface
Pin List Sorted by PGA Location
SysDataL28
14Hardware Interface
BcDataH70 SysDataL5
16Hardware Interface
Ground and Power VSS and VDD Pin List
Mechanical Specifications
Mechanical Specifications
21264/EV68A Packaging
21264/EV68A Packaging
18Hardware Interface
21264/EV68A Bottom View Pin Up
Page
Introduction to the External Interfaces
Cache and External Interfaces
Cache and External Interfaces
Introduction to the External Interfaces
21264/EV68A System and Bcache Interfaces
System Interface
Physical Address Considerations
Commands and Addresses
Physical Address Considerations
Second-Level Cache Bcache Interface
MB/WMB
ECB I/O
Physical Address Considerations
Bcache Structure
Bcache Interface Signals
Bcache Structure
System Duplicate Tag Stores
Cache Coherency
Victim Data Buffer
Victim Data Buffer
Cache Coherency Basics
Cache Block States
Cache Coherency
2lists the cache block states supported by the 21264/EV68A
21264/EV68A-Supported Cache Block States
System Responses to 21264/EV68A Commands
Mands. -4lists these commands
Cache Block State Transitions
Cache Block State Transitions
System Responses to 21264/EV68A Commands and Reactions
Using SysDc Commands
12Cache and External Interfaces
Dcache States and Duplicate Tags
Lock Mechanism
Lock Mechanism
14Cache and External Interfaces
Internal Eviction of LDxL Blocks
In-Order Processing of LDxL/STxC Instructions
Liveness and Fairness
System Port
System Port
16Cache and External Interfaces
System Port Pins
System Port Pins
Programming Values for System Interface Clocks
Programming the System Interface Clocks
Program Values for Data-Sample/Drive CSRs
18Cache and External Interfaces
Bank Interleave on Cache Block Boundary Mode
3 21264/EV68A-to-System Commands
Forwarded Clocks and Frame Clock Ratio
11 Page Hit Mode of Operation
Hit Mode
12 21264/EV68A-to-System Command Fields Definitions
12describes the field definitions for Tables 4-10and
14describes the 21264/EV68A-to-system commands
4 21264/EV68A-to-System Commands Descriptions
14 21264/EV68A-to-System Commands Descriptions
13 Maximum Physical Address for Short Bus Format
22Cache and External Interfaces
15 Programming INVALTODIRTYENABLE10
16 Programming SETDIRTYENABLE20
ProbeResponse Commands Command40 =
17 21264/EV68A ProbeResponse Command
24Cache and External Interfaces
18describes the ProbeResponse command fields
SysAck and 21264/EV68A-to-System Commands Flow Control
18 ProbeResponse Fields Descriptions
Probe Commands Four Cycles
System-to-21264/EV68A Commands
19 System-to-21264/EV68A Probe Commands
RVB RPB
21 lists the data movement selected by Probe43
20 System-to-21264/EV68A Probe Commands Fields Descriptions
22lists the next cache block state selected by Probe20
21 Data Movement Selection by Probe43
23 Data Transfer Command Format
Data Transfer Commands Two Cycles
28Cache and External Interfaces
24 SysDc40 Field Description
24describes the SysDc40 field
8.1 21264/EV68A Clock Basics
Data Movement In and Out of the 21264/EV68A
30Cache and External Interfaces
Fast Data Mode
32Cache and External Interfaces
25 Sysclk Cycles Between SysAddOut and SysData
26 Cbox CSR SYSDCDELAY40 Examples
26shows four example configurations and shows their use
Fast Data Disable Mode
SysDataInValidL and SysDataOutValidL
27 Four Timing Examples
SysDataInValidL
34Cache and External Interfaces
SysFillValidL
SysDataOutValidL
28 Data Wrapping Rules
Data Wrapping
36Cache and External Interfaces
29 System Wrap and Deliver Data
30defines the interleaved scheme for the wrap order
30 Wrap Interleave Order
31defines the wrap order for double-pumped data trans fers
Nonexistent Memory Processing
31 Wrap Order for Double-Pumped Data Transfers
38Cache and External Interfaces
21264/EV68A Command NXM Address System/21264/EV68A Response
Ordering of System Port Transactions
10.1 21264/EV68A Commands and System Probes
40Cache and External Interfaces
System Port
Bcache Port
Bcache Port
36 Bcache Port Pins
Bcache Port Pins
35 Range of Maximum Bcache Clock Ratios
44Cache and External Interfaces
Bcache Clocking
38 BCCLKDELAY10 Values
37 BCCPUCLKDELAY10 Values
Setting the Period of the Cache Clock
46Cache and External Interfaces
39 Program Values to Set the Cache Clock Period Single-Data
41 Data-Sample/Drive Cbox CSRs
Bcache Transactions
Bcache Data Read and Tag Read Transactions
48Cache and External Interfaces
Bcache Data Write Transactions
When the ratio is odd, bcfrm is twice the ratio
When the ratio is even, bcfrm is equal to the ratio
For example, in single-data mode
Dual-data mode, bcfrm is twice the ratio
Relationship Between Write-to-Read Bcwrrdbubbles and wrrd
Pin Descriptions
Relationship Between Read-to-Write Bcrdwrbubbles and rdwr
50Cache and External Interfaces
43 Programming the Bcache Control Pins
Bcache Control Pins
44 lists the combination of control pin assertion for
BcAddH234
46 Control Pin Assertion for Ramtype C
45 Control Pin Assertion for Ramtype B
47 Control Pin Assertion for Ramtype D
52Cache and External Interfaces
Disabling the Bcache for Debugging
Bcache Banking
BcDataInClkH and BcTagInClkH
Interrupts
Interrupts
54Cache and External Interfaces
Internal Processor Registers
Internal Processor Registers
Mbox IPRs
Ebox IPRs
Ebox IPRs
Cycle Counter Register CC
Cycle Counter Control Register Ccctl
Virtual Address Control Register Vactl
Virtual Address Register VA
2describes the Ccctl register fields
Cycle Counter Control Register Fields Description
3describes the virtual address control register fields
Virtual Address Format Register Vaform
Virtual Address Control Register Fields Description
VAFORM32
Ibox IPRs
Ibox IPRs
ITB Tag Array Write Register Itbtag
ITB PTE Array Write Register Itbpte
ITB Invalidate All Register Itbia
ITB Invalidate All Process ASM=0 Register Itbiap
ITB Invalidate Single Register Itbis
Exception Address Register Excaddr
ProfileMe PC Register Pmpc
4describes the ProfileMe PC register fields
ProfileMe PC Fields Description
Instruction Virtual Address Format Register Ivaform
Interrupt Enable and Current Processor Mode Register Iercm
Iercm Register Fields Description
Software Interrupt Request Register Sirr
10Internal Processor Registers
6describes the software interrupt request register fields
Interrupt Summary Register Isum
Software Interrupt Request Register Fields Description
7describes the interrupt summary register fields
Hardware Interrupt Clear Register Hwintclr
Interrupt Summary Register Fields Description
12Internal Processor Registers
8describes the hardware interrupt clear register fields
Exception Summary Register Excsum
Hardware Interrupt Clear Register Fields Description
Mchkd W1C
Exception Summary Register Fields Description
9describes the exception summary register fields
14Internal Processor Registers
Ibox Control Register Ictl
PAL Base Register Palbase
10describes the PAL base register fields
10 PAL Base Register Fields Description
11 Ibox Control Register Fields Description
11describes the Ibox control register fields
16Internal Processor Registers
STWAIT64K
Singleissueh
PCT1EN
PCT0EN
Spce
Ibox Status Register Istat
18Internal Processor Registers
12 Ibox Status Register Fields Description
12describes the Ibox status register fields
MIS
TRP
20Internal Processor Registers
Icache Flush Register Icflush
Sleep Mode Register Sleep
Icache Flush ASM Register Icflushasm
Clear Virtual-to-Physical Map Register Clrmap
14 Process Context Register Fields Description
14describes the process context register fields
22Internal Processor Registers
15describes the performance counter control register fields
Performance Counter Control Register Pctrctl
15 Performance Counter Control Register Fields Description
Pmstalled
Pctxppce
Pmkilledbm
SL0
Mbox IPRs
Mbox IPRs
DTB Tag Array Write Registers 0 and 1 DTBTAG0, DTBTAG1
16 Performance Counter Control Register Input Select Fields
17 DTB Alternate Processor Mode Register Fields Description
DTB Alternate Processor Mode Register Dtbaltmode
DTB PTE Array Write Registers 0 and 1 DTBPTE0, DTBPTE1
17describes the Dtbaltmode register fields
Dstream TB Invalidate All Register Dtbia
Dstream TB Invalidate All Process ASM=0 Register Dtbiap
Dstream TB Invalidate Single Registers 0 and 1 DTBIS0,1
ALTMODE10
Memory Management Status Register Mmstat
Dstream TB Address Space Number Registers 0 and 1 DTBASN0,1
18describes the memory management status register fields
18 Memory Management Status Register Fields Description
For
Mbox Control Register Mctl
ACV
Dcache Control Register Dcctl
Erences to superpages result in access violations
19describes the Mbox control register fields
19 Mbox Control Register Fields Description
20describes the Dcache control register fields
Dcache Status Register Dcstat
20 Dcache Control Register Fields Description
Cbox CSRs and IPRs
Cbox CSRs and IPRs
21describes the Dcache status register fields
21 Dcache Status Register Fields Description
Cbox Shift Register Cshft
Cbox Data Register Cdata
Cbox Writeonce Chain Description
22 describes the Cbox data register fields
34Internal Processor Registers
24 Cbox Writeonce Chain Order
Mboxbcprbstall BCLATDATAPATTERN031 BCLATTAGPATTERN023
BCWRRDBUBBLES03
36Internal Processor Registers
SYSCLKDELAY10
38Internal Processor Registers
Cbox Writemany Chain Description
25 Cbox Writemany Chain Order
40Internal Processor Registers
26 Cbox Read IPR Fields Description
Cbox Read Register IPR Description
0 1 1 Istreammemerr
0 1 1 Dstreammemerr
PALcode Description
Privileged Architecture Library Code
Privileged Architecture Library Code
PALmode Environment
PALmode Environment
Opcodes Reserved for PALcode
Required PALcode Function Codes
Required PALcode Function Codes
Hwld Instruction
Hwst Instruction
Opcodes Reserved for PALcode
3describes the Hwld instruction fields
Hwld Instruction Fields Descriptions
4describes the Hwst instruction fields
Hwret Instruction
Hwst Instruction Fields Descriptions
5describes the Hwret instruction fields
Hwmfpr and Hwmtpr Instructions
Hwret Instruction Fields Descriptions
Hint
Internal Processor Register Access Mechanisms
Internal Processor Register Access Mechanisms
6describes the Hwmfpr and Hwmtpr instructions fields
Hwmfpr and Hwmtpr Instructions Fields Descriptions
Hardware Structure of Explicitly Written IPRs
IPR Scoreboard Bits
Hardware Structure of Implicitly Written IPRs
IPR Access Ordering
Paired Instruction Fetch Order
10Privileged Architecture Library Code
PALcode Emulation of the Fpcr
PALshadow Registers
PALshadow Registers
PALcode Entry Points
PALcode Entry Points
PALcode Exception Entry Locations
PALcode Exception Entry Points
Translation Buffer TB Fill Flows
Translation Buffer TB Fill Flows
DTB Fill
14Privileged Architecture Library Code
Tb miss
Wr Data
Wr PTE LD-PTE, write TB
16Privileged Architecture Library Code
ITB Fill
Performance Counter Support
Performance Counter Support
Aggregate Mode Programming Guidelines
General Precautions
Aggregate Mode Precautions
IPRs Used for Performance Counter Support
Operation
10 Aggregate Mode Returned IPR Contents
Pctrctl SL0
SL1
11shows the counter modes that are used with Aggregate mode
ProfileMe Mode Programming Guidelines
This input counts Mbox replay traps
12 Cmov Decomposed
22Privileged Architecture Library Code
13 ProfileMe Mode Returned IPR Contents
Inum retire delay cycles
ProfileMe Counting Mode Description Cycle counting
Counter Modes for ProfileMe Mode
14shows the counter modes that are used with ProfileMe mode
14 ProfileMe Mode Pctrctl Input Select Fields
24Privileged Architecture Library Code
Power-Up Reset Flow and the ResetL and Dcokh Pins
Initialization and Configuration
21264/EV68A Reset State Machine Major Operations
Initialization and Configuration
Constraints
Power-Up Reset Flow and the ResetL and Dcokh Pins
Signal Pin Reset State
Power Sequencing and Reset State for Signal Pins
Pllvdd
Clock Forwarding and System Clock Ratio Configuration
PLL
Pin Signal Names and Initialization State
BiST and Srom Load and the TestStatH Pin
PLL Ramp Up
Power-Up Flow Signals and Their Constraints
Clock Forward Reset and System Interface Initialization
EV68A
Fault Reset Flow
Fault Reset Flow
Effect on IPRs After Fault Reset
Energy Star Certification and Sleep Mode Flow
Energy Star Certification and Sleep Mode Flow
10Initialization and Configuration
Effect on IPRs After Transition Through Sleep Mode
Warm Reset Flow
Warm Reset Flow
Signals and Constraints for the Sleep Mode Sequence
Effect on IPRs After Warm Reset
12Initialization and Configuration
Initialization Mode Processing
Array Initialization
Array Initialization
Evictenable BCWRTSTS30 Bcbankenable
Initialization Mode Processing
10 Internal Processor Registers at Power-Up Reset State
Internal Processor Register Power-Up Reset State
14Initialization and Configuration
External Interface Initialization
Internal Processor Register Power-Up Reset State
Reset State Machine
Ieee 1149.1 Test Port Reset
Ieee 1149.1 Test Port Reset
16Initialization and Configuration
11 21264/EV68A Reset State Machine State Descriptions
Reset State Machine
18Initialization and Configuration
Phase-Lock Loop PLL Functional Description
Phase-Lock Loop PLL Functional Description
Differential Reference Clocks
PLL Output Clocks
20Initialization and Configuration
Power-Up/Reset Clocking
21264/EV68A Error Detection Mechanisms
Error Detection and Error Handling
Error Detection and Error Handling
Icache Data or Tag Parity Error
Data Error Correction Code
Dcache Tag Parity Error
Data Error Correction Code
Dcache Data Single-Bit Correctable ECC Error
Dcache Data Single-Bit Correctable ECC Error
Load Instruction
Dcache Duplicate Tag Parity Error
Dcache Store Second Error
Dcache Store Second Error
Store Instruction Quadword or Smaller
Bcache Data Single-Bit Correctable ECC Error
Bcache Tag Parity Error
Bcache Tag Parity Error
Controlling Bcache Block Parity Calculation
Dcache Fill from Bcache
Bcache Data Single-Bit Correctable ECC Error
Memory/System Port Single-Bit Data Correctable ECC Error
Memory/System Port Single-Bit Data Correctable ECC Error
Bcache Victim Read
Icache Fill from Memory
Dcache Fill from Memory
Double-Bit Fill Errors
Bcache Data Single-Bit Correctable ECC Error on a Probe
Bcache Data Single-Bit Correctable ECC Error on a Probe
Error Case Summary
Error Case Summary
3summarizes the various error cases and their ramifications
Section D.36
Cstatdstreammemerr
Mchk Cstatistreammemerr
CRD Cstatprobebcerr
Mchk Cstatistreambcdbl
Page
Electrical Data
Electrical Characteristics
1lists the maximum electrical ratings for the 21264/EV68A
Maximum Electrical Ratings
DC Characteristics
DC Characteristics
Signal Types
Idcpower
Input DC Reference Pin Idcref
VDD Idcpower
Input Differential Amplifier Receiver IDA
Input Differential Amplifier Clock Receiver Idaclk
Pin Type Open-Drain Output Driver OOD
Pin Type Open-Drain Driver for Test Pins Oodtp
IOZ
Codtp
12 Push-Pull Output Clock Driver Oppclk
11 Push-Pull Output Driver OPP
AC Characteristics
AC Characteristics
AC Test Conditions
TSU1 TDH2
13 AC Specifications
Dcokh
AC Characteristics
Page
Operating Temperature at Heat Sink Center Tc
Operating Temperature
Thermal Management
That causes thermal failure
Θca at Various Airflows for 21264/EV68A
Operating Temperature
10-2Thermal Management
Heat Sink Specifications
Heat Sink Specifications
10-4Thermal Management
Type 2 Heat Sink
Type 3 Heat Sink
Thermal Design Considerations
Thermal Design Considerations
10-6Thermal Management
Test Pins
Testability and Diagnostics
Dedicated Test Port Pins
Testability and Diagnostics
SROM/Serial Diagnostic Terminal Port
SROM/Serial Diagnostic Terminal Port
11-2Testability and Diagnostics
Srom Load Operation
Ieee 1149.1 Port
Ieee 1149.1 Port
Ieee 1149.1 Instructions and Opcodes
TestStatH Pin
11-4Testability and Diagnostics
TestStatH Pin
TAP Controller State Machine
Power-Up Self-Test and Initialization
Power-Up Self-Test and Initialization
Built-in Self-Test
Srom Initialization
Serial Instruction Cache Load Operation
11-6Testability and Diagnostics
Icache Bit Fields in an Srom Line
See Appendix B for a listing of the Boundary-Scan Register
References
Page
Alpha Instruction Summary
Alpha Instruction Set
Table A-1 Instruction Format and Opcode Notation
Alpha Instruction Set A-1
Alpha Instruction Summary
Pcd Trap to PALcode
Mbr Branch to subroutine
Opr 11.24 Cmove if = zero
Opr 11.46 Cmove if ≥ zero
17.010 Convert longword to quadword
15.0AF Convert Gfloating to quadword
15.0BC Convert quadword to Ffloating
15.0BE Convert quadword to Gfloating
17.02E Fcmove if ≤ zero
17.02F Fcmove if zero
17.02C Fcmove if zero
17.02B Fcmove if ≠ zero
Opr 13.60 Multiply quadword with integer overflow enable
Opr 13.40 Multiply longword with integer overflow enable
Opr 1C.31 Pixel error
Mem Load Sfloating
Mbr 1A.2 Return from subroutine
Opr 1C.36 Pack words to bytes Mfc 18.E000 Read and clear
Mfc 18.C000 Read process cycle counter 18.F000 Read and set
Opr 10.02 Scaled add longword by
Reserved Opcodes
Reserved Opcodes
Opcodes Reserved for Compaq
Ieee Floating-Point Instructions
Ieee Floating-Point Instructions
Opcodes Reserved for PALcode
18B 10B 14B
08B 00B 04B
02B 06B
12B 16B
Independent Floating-Point Instructions
VAX Floating-Point Instructions
VAX Floating-Point Instructions
Opcode Summary
Opcode Summary
Mem Res
Mem Table A-9explains the symbols used in Table A-8
Ieee floating-point instruction opcodes
Floating-point operate instruction opcodes
Ieee Floating-Point Conformance
Ieee Floating-Point Conformance
14Alpha Instruction Set
Alpha Instruction Set A-15
Table A-11 Exceptional Input and Output Conditions
16Alpha Instruction Set
Cmptlt Cmptle Input
Cmpteq Cmptun Input
Alpha Instruction Set A-17
Fbeq Fbne Fblt Fble Fbgt Fbge LDS LDT STS STT Cpys Cpysn
Boundary-Scan Register
21264/EV68A Boundary-Scan Register
Pllvdd
Boundary-Scan Register
21264/EV68A Boundary-Scan Register B-3
421264/EV68A Boundary-Scan Register
21264/EV68A Boundary-Scan Register B-5
621264/EV68A Boundary-Scan Register
21264/EV68A Boundary-Scan Register B-7
821264/EV68A Boundary-Scan Register
21264/EV68A Boundary-Scan Register B-9
1021264/EV68A Boundary-Scan Register
21264/EV68A Boundary-Scan Register B-11
1221264/EV68A Boundary-Scan Register
Serial Icache Load Predecode Values C-1
Serial Icache Load Predecode Values
Page
PALcode Restrictions and Guidelines D-1
PALcode Restrictions and Guidelines
2PALcode Restrictions and Guidelines
PALcode Restrictions and Guidelines D-3
4PALcode Restrictions and Guidelines
Initwritemany
PALcode Restrictions and Guidelines D-5
6PALcode Restrictions and Guidelines
PALcode Restrictions and Guidelines D-7
8PALcode Restrictions and Guidelines
PALcode Restrictions and Guidelines D-9
Restriction 7 Replay Trap, Interrupt Code Sequence, and STF
Restriction 9 PALmode Istream Address Ranges
Restriction 10 Duplicate IPR Mode Bits
Restriction 9 PALmode Istream Address Ranges
10PALcode Restrictions and Guidelines
Restriction 11 Ibox IPR Update Synchronization
Restriction 11 Ibox IPR Update Synchronization
Restriction 13 DTB Fill Flow Collision
Restriction 14 Hwret
Guideline 16 JSR-BAD VA
Guideline 20 Ictlsbe Stream Buffer Enable
Restriction 21 HWRET/STALL After Hwmtpr ASN0/ASN1
Guideline 16 JSR-BAD VA
Restriction 22 HWRET/STALL After Hwmtpr IS0/IS1
Restriction 22 HWRET/STALL After Hwmtpr IS0/IS1
PALcode Restrictions and Guidelines D-13
Guideline 26 Conditional Branches in PALcode
Restriction 25 Hwmtpr Itbia After Reset
Restriction 24 HWRET/STALL After Hwmtpr ICFLUSH, Icflushasm
14PALcode Restrictions and Guidelines
Restriction 30 Hwmtpr and Hwmfpr to the Cbox CSR
Guideline 29 JSR, JMP, RET, and Jsrcor in PALcode
PALcode Restrictions and Guidelines D-15
16PALcode Restrictions and Guidelines
Restriction 30 Hwmtpr and Hwmfpr to the Cbox CSR
Restriction 32 Pctrctl Update
Restriction 31 ICTLVA48 Update
Restriction 31 ICTLVA48 Update
PALcode Restrictions and Guidelines D-17
Restriction 33 Hwld Physical/Lock Use
Guideline 35 Hwintclr Update
Restriction 36 Updating Ictlsde
Restriction 37 Updating VACTLVA48
PALcode Restrictions and Guidelines D-19
Restriction 40 Scrubbing a Single-Bit Error
20PALcode Restrictions and Guidelines
Restriction 40 Scrubbing a Single-Bit Error
Restriction 43 No Trappable Instructions Along with
Restriction 42 Updating VACTL, CCCTL, or CC IPRs
PALcode Restrictions and Guidelines D-21
22PALcode Restrictions and Guidelines
Restriction 47 Cache Eviction for Single-Bit Cache Errors
PALcode Restrictions and Guidelines D-23
Restriction 47 Cache Eviction for Single-Bit Cache Errors
24PALcode Restrictions and Guidelines
Forwarding Clock Pin Groupings
21264/EV68A-to-Bcache Pin Interface
Table E-1 Bcache Forwarding Clock Pin Groupings
Late-Write Non-Bursting SSRAMs
Late-Write Non-Bursting SSRAMs
Data Pin Usage
Tag Pin Usage
Dual-Data Rate SSRAMs
Dual-Data Rate SSRAMs
Table E-4 Dual-Data Rate Ssram Data Pin Usage
Table E-5 Dual-Data Rate Ssram Tag Pin Usage
Trstl
421264/EV68A-to-Bcache Pin Interface
21264/EV68A-to-Bcache Pin Interface E-5
Page
Glossary
BIU
BSR
Cisc
CPI
Cmos
CPU
CSR
Dram
DMA
DTB
DTL
FET
Feprom
FEU
Fpga
IDU
Gclk
Ipga
Iowb
ITB
Jfet
MBO
MAF
MBZ
Mips
Naturally Aligned
MSI
Nmos
Nvram
PGA
PAL
PLA
Plcc
Prom
Pqfp
RAM
RAS
ROM
Risc
RTL
SAM
Simm
Sdram
SIP
Sipp
TTL
Stram
Uart
Unaligned
Uvprom
Unpredictable
VAF
VDF
Writeblock
WAR
Numerics
Index
Index-2
Index-3
Index-4
ECC
Index-6
Index-7
Index-8
Index-9
Index-10
Index-11
Index-12
