Compaq EV68A SROM/Serial Diagnostic Terminal Port, Srom Load Operation, Serial Terminal Port

SROM/Serial Diagnostic Terminal Port

Table 11–1 Dedicated Test Port Pins (Continued)

Pin Name	Type	Function
SromClk_H	Output	SROM clock/Diagnostic terminal data output
SromOE_L	Output	SROM enable/Diagnostic terminal enable
TestStat_H	Output	BiST status/timeout output

11.2 SROM/Serial Diagnostic Terminal Port

This port supports two functions. During power-up, it supports automatic initialization of the Cbox configuration registers and the Icache from the system serial ROMs. After power-up, it supports a serial diagnostic terminal.

11.2.1 SROM Load Operation

The following actions are performed while the SROM is loaded:

•The SromOE_L pin supplies the output enable as well as the reset to the serial ROM. (Refer to the serial ROM specifications for details.) The 21264/EV68A asserts this signal low for the duration of the Icache load from the serial ROM. When the load has been completed, the signal remains deasserted.

•The SromClk_H pin supplies the clock to the SROM that causes it to advance to the next bit. Simultaneously, it causes the existing data on the SromData_H pin to be shifted into an internal shift register. The cycle time of this clock is 256 times the CPU clock rate. (If the FASTROM flag is set, the rate is 16 times the CPU clock rate.) The hold time on SromData_H is 2* CPU cycle time with respect to SromClk_H.

•The SromData_H pin reads data from the SROM.

Every data and tag bit in Icache is loaded by that sequence.

11.2.2 Serial Terminal Port

After the SROM data is loaded into the Icache, the three SROM interface signals can be used as a software UART and the pins become parallel I/O pins that can drive a system debug or diagnostic terminal by using an interface such as RS422.

The serial line interface is automatically enabled if the SromOE_L pin is wired to the following pins:

•An active high enable RS422 (or 26LS32) driver, driving to SromData_H

•An active high enable RS422 (or 26LS31) receiver, driven from SromClk_H

After reset, SromClk_H is driven from the Ibox I_CTL[SL_XMIT]. This register is cleared during reset, so it starts driving as a 0, but it can be written by software. The data becomes available at the pin after the HW_MTPR instruction that wrote I_CTL[SL_XMIT] is retired.

11–2Testability and Diagnostics 21264/EV68A Hardware Reference Manual