Compaq EV68A specifications Initialization and Configuration, Mffpcr Mtfpcr

	6.5.3		Hardware Structure of Implicitly Written IPRs	6–9
	6.5.4		IPR Access Ordering	6–9
	6.5.5		Correct Ordering of Explicit Writers Followed by Implicit Readers	6–10
	6.5.6		Correct Ordering of Explicit Readers Followed by Implicit Writers	6–11
	6.6	PALshadow Registers		6–11
	6.7	PALcode Emulation of the FPCR		6–11
	6.7.1		Status Flags	6–12
	6.7.2		MF_FPCR	6–12
	6.7.3		MT_FPCR	6–12
	6.8	PALcode Entry Points		6–12
	6.8.1		CALL_PAL Entry Points	6–12
	6.8.2		PALcode Exception Entry Points	6–13
	6.9	Translation Buffer (TB) Fill Flows		6–14
	6.9.1		DTB Fill	6–14
	6.9.2		ITB Fill	6–16
	6.10	Performance Counter Support		6–17
	6.10.1		General Precautions	6–18
	6.10.2		Aggregate Mode Programming Guidelines	6–18
	6.10.2.1		Aggregate Mode Precautions	6–18
	6.10.2.2		Operation	6–19
	6.10.2.3		Aggregate Counting Mode Description	6–20
	6.10.2.3.1		Cycle counting	6–20
	6.10.2.3.2		Retired instructions cycles	6–20
	6.10.2.3.3		Bcache miss or long latency probes cycles	6–20
	6.10.2.3.4		Mbox replay traps cycles	6–20
	6.10.2.4		Counter Modes for Aggregate Mode	6–20
	6.10.3		ProfileMe Mode Programming Guidelines	6–20
	6.10.3.1		ProfileMe Mode Precautions	6–20
	6.10.3.2		Operation	6–21
	6.10.3.3		ProfileMe Counting Mode Description	6–23
	6.10.3.3.1		Cycle counting	6–23
	6.10.3.3.2		Inum retire delay cycles	6–23
	6.10.3.3.3		Retired instructions cycles	6–23
	6.10.3.3.4		Bcache miss or long latency probes cycles	6–23
	6.10.3.3.5		Mbox replay traps cycles	6–23
	6.10.3.4		Counter Modes for ProfileMe Mode	6–24
7	Initialization and Configuration
	7.1	Power-Up Reset Flow and the Reset_L and DCOK_H Pins		7–1
	7.1.1		Power Sequencing and Reset State for Signal Pins	7–3
	7.1.2		Clock Forwarding and System Clock Ratio Configuration	7–4
	7.1.3		PLL Ramp Up	7–6
	7.1.4		BiST and SROM Load and the TestStat_H Pin	7–6
	7.1.5		Clock Forward Reset and System Interface Initialization	7–7
	7.2	Fault Reset Flow		7–8
	7.3	Energy Star Certification and Sleep Mode Flow		7–9
	7.4	Warm Reset Flow		7–11
	7.5	Array Initialization		7–12
	7.6	Initialization Mode Processing		7–12
	7.7	External Interface Initialization		7–14
	7.8	Internal Processor Register Power-Up Reset State		7–14
	7.9	IEEE 1149.1 Test Port Reset		7–16
	7.10	Reset State Machine		7–16
	7.11	Phase-Lock Loop (PLL) Functional Description		7–19
	7.11.1		Differential Reference Clocks	7–19
	7.11.2		PLL Output Clocks	7–19

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