Compaq EV68A specifications VDD Idcpower

7–6	Effect on IPRs After Transition Through Sleep Mode	7–10
7–7	Signals and Constraints for the Sleep Mode Sequence	7–11
7–8	Effect on IPRs After Warm Reset	7–11
7–9	WRITE_MANY Chain CSR Values for Bcache Initialization	7–12
7–10	Internal Processor Registers at Power-Up Reset State	7–14
7–11	21264/EV68A Reset State Machine State Descriptions	7–17
7–12	Differential Reference Clock Frequencies in Full-Speed Lock	7–20
8–1	21264/EV68A Error Detection Mechanisms	8–1
8–2	64-Bit Data and Check Bit ECC Code	8–2
8–3	Error Case Summary	8–10
9–1	Maximum Electrical Ratings	9–1
9–2	Signal Types	9–2
9–3	VDD (I_DC_POWER)	9–3
9–4	Input DC Reference Pin (I_DC_REF)	9–3
9–5	Input Differential Amplifier Receiver (I_DA)	9–3
9–6	Input Differential Amplifier Clock Receiver (I_DA_CLK)	9–3
9–7	Pin Type: Open-Drain Output Driver (O_OD)	9–4
9–8	Bidirectional, Differential Amplifier Receiver, Open-Drain Output Driver (B_DA_OD)	9–4
9–9	Pin Type: Open-Drain Driver for Test Pins (O_OD_TP)	9–4
9–10	Bidirectional, Differential Amplifier Receiver, Push-Pull Output Driver (B_DA_PP)	9–4
9–11	Push-Pull Output Driver (O_PP)	9–5
9–12	Push-Pull Output Clock Driver (O_PP_CLK)	9–5
9–13	AC Specifications	9–7
10–1	Operating Temperature at Heat Sink Center (Tc)	10–1
10–2	qca at Various Airflows for 21264/EV68A	10–2
10–3	Maximum Ta for 21264/EV68A @ 750 MHz and @ 1.7 V with Various Airflows	10–2
10–4	Maximum Ta for 21264/EV68A @ 833 MHz and @ 1.7 V with Various Airflows	10–2
10–5	Maximum Ta for 21264/EV68A @ 875 MHz and @ 1.7 V with Various Airflows	10–2
10–6	Maximum Ta for 21264/EV68A @ 940 MHz and @ 1.7 V with Various Airflows	10–2
11–1	Dedicated Test Port Pins	11–1
11–2	IEEE 1149.1 Instructions and Opcodes	11–3
11–3	TAP Controller State Machine	11–4
11–4	Icache Bit Fields in an SROM Line	11–7
A–1	Instruction Format and Opcode Notation	A–1
A–2	Architecture Instructions	A–2
A–3	Opcodes Reserved for Compaq	A–8
A–4	Opcodes Reserved for PALcode	A–9
A–5	IEEE Floating-Point Instruction Function Codes	A–9
A–6	VAX Floating-Point Instruction Function Codes	A–11
A–7	Independent Floating-Point Instruction Function Codes	A–12
A–8	Opcode Summary	A–12
A–9	Key to Opcode Summary Used in Table A–8	A–13
A–10	Required PALcode Function Codes	A–13
A–11	Exceptional Input and Output Conditions	A–15
E–1	Bcache Forwarding Clock Pin Groupings	E–1
E–2	Late-WriteNon-Bursting SSRAMs Data Pin Usage	E–2
E–3	Late-WriteNon-Bursting SSRAMs Tag Pin Usage	E–2
E–4	Dual-Data Rate SSRAM Data Pin Usage	E–3
E–5	Dual-Data Rate SSRAM Tag Pin Usage	E–4

21264/EV68A Hardware Reference Manual xv