Compaq EV68A Ebox IPRs, Cycle Counter Register CC, Cycle Counter Control Register Ccctl

Ebox IPRs

Table 5–1 Internal Processor Registers (Continued)

				MT/MF	Latency
			Score-	Issued	for
		Index	Board	from Ebox	MFPR
Register Name	Mnemonic	(Binary)	Bit	Access Pipe	(Cycles)

Cbox IPRs

Cbox data	C_DATA	0010 1011	6	RW	0L	3
Cbox shift control	C_SHFT	0010 1100	6	WO	0L	Ò

1When n equals 1, that process context field is selected (FPE, PPCE, ASTRR, ASTER, ASN).

5.1 Ebox IPRs

This section describes the internal processor registers that control Ebox functions.

5.1.1 Cycle Counter Register – CC

The cycle counter register (CC) is a read-write register. The lower half of CC is a counter that, when enabled by way of CC_CTL[32], increments once each CPU cycle. The upper half of the register is 32 bits of register storage that may be used as a counter offset as described in the Alpha Architecture Handbook, Version 4 under Processor Cycle Counter (PCC) Register.

A HW_MTPR instruction to the CC writes the upper half of the register and leaves the lower half unchanged. The RPCC instruction returns the full 64-bit value of the register. Figure 5–1shows the cycle counter register.

Figure 5–1 Cycle Counter Register

63 32 31 0

OFFSET

COUNTER

5.1.2 Cycle Counter Control Register – CC_CTL

LK99-0008A

The cycle counter control register (CC_CTL) is a write-only register through which the lower half of the CC register may be written and its associated counter enabled and dis- abled. Figure 5–2shows the cycle counter control register.

Figure 5–2 Cycle Counter Control Register

63 33 32 31 4 3 0

CC_ENA

COUNTER[31:4]

LK99-0009A

21264/EV68A Hardware Reference Manual Internal Processor Registers 5–3