Nonexistent Memory Processing | Compaq EV68A instruction

System Port

Table 4–30 Wrap Interleave Order		(Continued)

		PA Bits [5:3] of Transferred QW

Sixth quadword	101	111	001	011
Seventh quadword	110	100	010	000
Eighth quadword	111	101	011	001

Table 4–31defines the wrap order for double-pumped data trans fers.

Table 4–31 Wrap Order for Double-Pumped Data Transfers

PA [5:3] of Transferred QW

First quadword	x00	x01	x10	x11
Second quadword	x00	x01	x10	x11
Third quadword	x01	x00	x11	x10
Fourth quadword	x01	x00	x11	x10
Fifth quadword	x10	x11	x00	x01
Sixth quadword	x10	x11	x00	x01
Seventh quadword	x11	x10	x01	x00
Eighth quadword	x11	x10	x01	x00

4.7.9 Nonexistent Memory Processing

Like its predecessors, the 21264/EV68A can generate references to nonexistent (NXM) memory or I/O space. However, unlike the earlier Alpha microprocessor implementa- tions, the 21264/EV68A can generate speculative references to memory space. To accommodate the speculative nature of the 21264/EV68A, the system must not gener- ate or lock error registers because of speculative references. The 21264/EV68A trans- lates all memory references through the translation lookaside buffer (TLB) and, in some cases, the 21264/EV68A may generate speculative references (instruction execution down mispredicted paths) to NXM space. In these cases, the system sends a SysDc ReadDataError and the 21264/EV68A does the following:

•Delivers an all-ones pattern to all load instructions to the NXM address

•Force-fails all store instructions to the NXM address (much like a STx_C failure)

•Invalidates the cache block at the same index by way of an atomic Evict command

4–38Cache and External Interfaces

21264/EV68A Hardware Reference Manual

Image 126

Compaq EV68A specifications Nonexistent Memory Processing, 31defines the wrap order for double-pumped data trans fers

Contents

Revision/Update Information Compaq Computer Corporation Shrewsbury, Massachusetts 21264/EV68A Hardware Reference Manual Table of Contents Hardware Interface Cache and External Interfaces Internal Processor Registers Privileged Architecture Library Code Initialization and Configuration Mffpcr Mtfpcr Electrical Data Error Detection and Error HandlingTestability and Diagnostics Thermal Management Alpha Instruction Set 21264/EV68A Boundary-Scan Register 21264/EV68A-to-Bcache Pin Interface Glossary Index Figures 10-2 Type 2 Heat Sink Tables Xiv VDD Idcpower Page Content PrefaceAudience Documentation Included by Reference Terminology and Conventions For exampleAbbreviations Addresses W1CW1S Aligned and Unaligned Do Not Care Signal NamesData Units External Undefined Do not care. a capital X represents any valid value Page Introduction ArchitectureIntroduction Integer Data Types ArchitectureAddressing Floating-Point Data Types 21264/EV68A Microprocessor Features 21264/EV68A Microprocessor Features 21264/EV68A Microprocessor Features Internal Architecture 21264/EV68A MicroarchitectureInternal Architecture Instruction Fetch, Issue, and Retire Unit 21264/EV68A MicroarchitectureVirtual Program Counter Logic 21264/EV68A Block Diagram Branch Predictor Local Predictor Global Predictor Choice Predictor Instruction-Stream Translation Buffer Integer Issue Queue Instruction Fetch LogicRegister Rename Maps Floating-Point Issue Queue Hwret Integer Execution Unit Exception and Interrupt LogicRetire Logic PERR, MINxxx, MAXxxx, UNPKxx, PKxx Integer Execution Unit-Clusters 0 Floating-Point Execution Unit 10Internal Architecture External Cache and System Interface Unit Onchip Caches21264/EV68A contains two onchip primary-level caches Memory Reference Unit Data Cache12Internal Architecture Srom Interface Pipeline OrganizationPipeline Organization Miss address file MAF Dstream translation buffer DTB Stage 0 Instruction Fetch Stage 1 Instruction Slot14Internal Architecture Stage 3 Issue Stage 2 Map Pipeline Aborts Instruction Issue RulesInstruction Issue Rules Ebox and Fbox pipelines begin execution Instruction Group Definitions Instruction Name, Pipeline, and Types ITOFS, ITOFF, Itoft Ebox SlottingFTOIS, Ftoit Instruction Group Definitions and Pipeline Unit U U L E L U E E L L E U Hwmfpr Instruction LatenciesInstruction Class Latency in Cycles 20Internal Architecture Instruction Retire Rules Instruction Retire RulesMinimum Retire Latencies for Instruction Classes Floating-Point Divide/Square Root Early Retire Retire of Operate Instructions into R31/F31Retire of Operate Instructions into R31/F31 BSR/JSR Prefetch with Modify Intent LDS Instruction Load Instructions to R31 and F31Load Instructions to R31 and F31 Instructions Retired Without Execution Prefetch, Evict Next LDQ and Hwldq Instructions Special Cases of Alpha Instruction ExecutionSpecial Cases of Alpha Instruction Execution Load Hit Speculation 10 Pipeline Timing for Floating-Point Load Instructions Floating-Point Store Instructions Cmov Instruction26Internal Architecture Memory Address Space Load Instructions Memory and I/O Address Space InstructionsMemory and I/O Address Space Instructions 2 I/O Address Space Load Instructions Memory Address Space Store Instructions Rules for I/O Address Space Load Instruction Data Merging28Internal Architecture 4 I/O Address Space Store Instructions Rules for I/O Address Space Store Instruction Data Merging MAF Memory Address Space Merging Rules Instruction OrderingMAF Memory Address Space Merging Rules Replay Traps Replay TrapsMbox Order Traps Other Mbox Replay Traps 12 I/O Write Buffer and the WMB InstructionWrite Buffer and the WMB Instruction Memory Barrier MB/WMB/TB Fill Flow MB Instruction Processing WMB Instruction Processing 13 TB Fill Flow Example Sequence TB Fill Flow12 TB Fill Flow Example Sequence 34Internal Architecture Performance Measurement Support-Performance Counters Performance Measurement Support-Performance CountersFloating-Point Control Register Floating-point control register Fpcr is shown in Figure Floating-Point Control Register 14 Floating-Point Control Register Fields36Internal Architecture Amask and Implver Instruction Values Amask and Implver Instruction Values Amask Design ExamplesDesign Examples Implver 12 Typical Uniprocessor Configuration Page 21264/EV68A Microprocessor Logic Symbol Hardware InterfaceHardware Interface 21264/EV68A Microprocessor Logic Symbol 21264/EV68A Microprocessor Logic Symbol Signal Pin Types Definitions 21264/EV68A Signal Names and Functions21264/EV68A Signal Names and Functions 21264/EV68A Signal Descriptions Dcokh Pllvdd 21264/EV68A Signal Descriptions by Function TestStatH SysVref Domain SysAddInL140 Pin List Sorted by Signal Name Pin AssignmentsPin Assignments AC1 10Hardware Interface Pllvdd AA5 Pin List Sorted by PGA Location 12Hardware Interface SysDataL28 14Hardware Interface BcDataH70 SysDataL5 Ground and Power VSS and VDD Pin List 16Hardware Interface Mechanical Specifications Mechanical Specifications 21264/EV68A Packaging 21264/EV68A Packaging18Hardware Interface 21264/EV68A Bottom View Pin Up Page Cache and External Interfaces Introduction to the External InterfacesCache and External Interfaces Introduction to the External Interfaces System Interface 21264/EV68A System and Bcache Interfaces Physical Address Considerations Commands and AddressesPhysical Address Considerations Second-Level Cache Bcache Interface ECB I/O MB/WMB Physical Address Considerations Bcache Structure Bcache Interface SignalsBcache Structure System Duplicate Tag Stores Victim Data Buffer Victim Data BufferCache Coherency Cache Coherency Basics 2lists the cache block states supported by the 21264/EV68A Cache CoherencyCache Block States 21264/EV68A-Supported Cache Block States Cache Block State Transitions Mands. -4lists these commandsSystem Responses to 21264/EV68A Commands Cache Block State Transitions Using SysDc Commands System Responses to 21264/EV68A Commands and Reactions 12Cache and External Interfaces Dcache States and Duplicate Tags Lock Mechanism Lock Mechanism14Cache and External Interfaces In-Order Processing of LDxL/STxC Instructions Internal Eviction of LDxL BlocksLiveness and Fairness System Port System Port16Cache and External Interfaces System Port Pins System Port Pins Program Values for Data-Sample/Drive CSRs Programming the System Interface ClocksProgramming Values for System Interface Clocks 18Cache and External Interfaces 3 21264/EV68A-to-System Commands Bank Interleave on Cache Block Boundary ModeForwarded Clocks and Frame Clock Ratio 12 21264/EV68A-to-System Command Fields Definitions Hit Mode11 Page Hit Mode of Operation 12describes the field definitions for Tables 4-10and 14 21264/EV68A-to-System Commands Descriptions 4 21264/EV68A-to-System Commands Descriptions14describes the 21264/EV68A-to-system commands 13 Maximum Physical Address for Short Bus Format 22Cache and External Interfaces 15 Programming INVALTODIRTYENABLE10 17 21264/EV68A ProbeResponse Command ProbeResponse Commands Command40 =16 Programming SETDIRTYENABLE20 24Cache and External Interfaces SysAck and 21264/EV68A-to-System Commands Flow Control 18describes the ProbeResponse command fields18 ProbeResponse Fields Descriptions 19 System-to-21264/EV68A Probe Commands System-to-21264/EV68A CommandsProbe Commands Four Cycles RVB RPB 22lists the next cache block state selected by Probe20 20 System-to-21264/EV68A Probe Commands Fields Descriptions21 lists the data movement selected by Probe43 21 Data Movement Selection by Probe43 Data Transfer Commands Two Cycles 23 Data Transfer Command Format28Cache and External Interfaces 24describes the SysDc40 field 24 SysDc40 Field Description Data Movement In and Out of the 21264/EV68A 8.1 21264/EV68A Clock Basics30Cache and External Interfaces Fast Data Mode 25 Sysclk Cycles Between SysAddOut and SysData 32Cache and External Interfaces 26shows four example configurations and shows their use 26 Cbox CSR SYSDCDELAY40 ExamplesFast Data Disable Mode SysDataInValidL 27 Four Timing ExamplesSysDataInValidL and SysDataOutValidL 34Cache and External Interfaces SysDataOutValidL SysFillValidL Data Wrapping 28 Data Wrapping Rules36Cache and External Interfaces 30defines the interleaved scheme for the wrap order 29 System Wrap and Deliver Data30 Wrap Interleave Order 31 Wrap Order for Double-Pumped Data Transfers Nonexistent Memory Processing31defines the wrap order for double-pumped data trans fers 38Cache and External Interfaces 21264/EV68A Command NXM Address System/21264/EV68A Response 10.1 21264/EV68A Commands and System Probes Ordering of System Port Transactions40Cache and External Interfaces System Port Bcache Port Bcache Port Bcache Port Pins 36 Bcache Port Pins35 Range of Maximum Bcache Clock Ratios Bcache Clocking 44Cache and External Interfaces 37 BCCPUCLKDELAY10 Values 38 BCCLKDELAY10 ValuesSetting the Period of the Cache Clock 39 Program Values to Set the Cache Clock Period Single-Data 46Cache and External Interfaces Bcache Transactions 41 Data-Sample/Drive Cbox CSRsBcache Data Read and Tag Read Transactions Bcache Data Write Transactions 48Cache and External Interfaces For example, in single-data mode When the ratio is even, bcfrm is equal to the ratioWhen the ratio is odd, bcfrm is twice the ratio Dual-data mode, bcfrm is twice the ratio Relationship Between Read-to-Write Bcrdwrbubbles and rdwr Pin DescriptionsRelationship Between Write-to-Read Bcwrrdbubbles and wrrd 50Cache and External Interfaces 44 lists the combination of control pin assertion for Bcache Control Pins43 Programming the Bcache Control Pins BcAddH234 47 Control Pin Assertion for Ramtype D 45 Control Pin Assertion for Ramtype B46 Control Pin Assertion for Ramtype C 52Cache and External Interfaces Bcache Banking Disabling the Bcache for DebuggingBcDataInClkH and BcTagInClkH Interrupts Interrupts54Cache and External Interfaces Internal Processor Registers Internal Processor Registers Mbox IPRs Cycle Counter Register CC Ebox IPRsEbox IPRs Cycle Counter Control Register Ccctl 2describes the Ccctl register fields Virtual Address Register VAVirtual Address Control Register Vactl Cycle Counter Control Register Fields Description Virtual Address Control Register Fields Description Virtual Address Format Register Vaform3describes the virtual address control register fields VAFORM32 ITB Tag Array Write Register Itbtag Ibox IPRsIbox IPRs ITB PTE Array Write Register Itbpte ITB Invalidate All Process ASM=0 Register Itbiap ITB Invalidate All Register ItbiaITB Invalidate Single Register Itbis 4describes the ProfileMe PC register fields ProfileMe PC Register PmpcException Address Register Excaddr ProfileMe PC Fields Description Interrupt Enable and Current Processor Mode Register Iercm Instruction Virtual Address Format Register Ivaform Software Interrupt Request Register Sirr Iercm Register Fields Description10Internal Processor Registers Interrupt Summary Register Isum 6describes the software interrupt request register fieldsSoftware Interrupt Request Register Fields Description Interrupt Summary Register Fields Description Hardware Interrupt Clear Register Hwintclr7describes the interrupt summary register fields 12Internal Processor Registers Hardware Interrupt Clear Register Fields Description Exception Summary Register Excsum8describes the hardware interrupt clear register fields Mchkd W1C 9describes the exception summary register fields Exception Summary Register Fields Description14Internal Processor Registers 10describes the PAL base register fields PAL Base Register PalbaseIbox Control Register Ictl 10 PAL Base Register Fields Description 11describes the Ibox control register fields 11 Ibox Control Register Fields Description16Internal Processor Registers PCT1EN SingleissuehSTWAIT64K PCT0EN Ibox Status Register Istat Spce18Internal Processor Registers MIS 12describes the Ibox status register fields12 Ibox Status Register Fields Description TRP 20Internal Processor Registers Icache Flush ASM Register Icflushasm Sleep Mode Register SleepIcache Flush Register Icflush Clear Virtual-to-Physical Map Register Clrmap 14describes the process context register fields 14 Process Context Register Fields Description22Internal Processor Registers Performance Counter Control Register Pctrctl 15describes the performance counter control register fields15 Performance Counter Control Register Fields Description Pmkilledbm PctxppcePmstalled SL0 DTB Tag Array Write Registers 0 and 1 DTBTAG0, DTBTAG1 Mbox IPRsMbox IPRs 16 Performance Counter Control Register Input Select Fields DTB PTE Array Write Registers 0 and 1 DTBPTE0, DTBPTE1 DTB Alternate Processor Mode Register Dtbaltmode17 DTB Alternate Processor Mode Register Fields Description 17describes the Dtbaltmode register fields Dstream TB Invalidate Single Registers 0 and 1 DTBIS0,1 Dstream TB Invalidate All Process ASM=0 Register DtbiapDstream TB Invalidate All Register Dtbia ALTMODE10 18describes the memory management status register fields Dstream TB Address Space Number Registers 0 and 1 DTBASN0,1Memory Management Status Register Mmstat 18 Memory Management Status Register Fields Description Mbox Control Register Mctl ForACV 19describes the Mbox control register fields Erences to superpages result in access violationsDcache Control Register Dcctl 19 Mbox Control Register Fields Description Dcache Status Register Dcstat 20describes the Dcache control register fields20 Dcache Control Register Fields Description 21describes the Dcache status register fields Cbox CSRs and IPRsCbox CSRs and IPRs 21 Dcache Status Register Fields Description Cbox Writeonce Chain Description Cbox Data Register CdataCbox Shift Register Cshft 22 describes the Cbox data register fields 24 Cbox Writeonce Chain Order 34Internal Processor Registers BCWRRDBUBBLES03 Mboxbcprbstall BCLATDATAPATTERN031 BCLATTAGPATTERN023 36Internal Processor Registers SYSCLKDELAY10 Cbox Writemany Chain Description 38Internal Processor Registers 25 Cbox Writemany Chain Order 40Internal Processor Registers Cbox Read Register IPR Description 26 Cbox Read IPR Fields Description 0 1 1 Dstreammemerr 0 1 1 Istreammemerr Privileged Architecture Library Code PALcode DescriptionPrivileged Architecture Library Code PALmode Environment PALmode Environment Required PALcode Function Codes Required PALcode Function CodesOpcodes Reserved for PALcode Hwld Instruction 3describes the Hwld instruction fields Opcodes Reserved for PALcodeHwst Instruction Hwld Instruction Fields Descriptions Hwret Instruction 4describes the Hwst instruction fieldsHwst Instruction Fields Descriptions Hwret Instruction Fields Descriptions Hwmfpr and Hwmtpr Instructions5describes the Hwret instruction fields Hint 6describes the Hwmfpr and Hwmtpr instructions fields Internal Processor Register Access MechanismsInternal Processor Register Access Mechanisms Hwmfpr and Hwmtpr Instructions Fields Descriptions IPR Scoreboard Bits Hardware Structure of Explicitly Written IPRs IPR Access Ordering Hardware Structure of Implicitly Written IPRsPaired Instruction Fetch Order 10Privileged Architecture Library Code PALshadow Registers PALcode Emulation of the FpcrPALshadow Registers PALcode Entry Points PALcode Entry Points PALcode Exception Entry Points PALcode Exception Entry Locations DTB Fill Translation Buffer TB Fill FlowsTranslation Buffer TB Fill Flows 14Privileged Architecture Library Code Wr Data Tb missWr PTE LD-PTE, write TB ITB Fill 16Privileged Architecture Library Code Performance Counter Support Performance Counter Support Aggregate Mode Precautions General PrecautionsAggregate Mode Programming Guidelines IPRs Used for Performance Counter Support Pctrctl SL0 10 Aggregate Mode Returned IPR ContentsOperation SL1 ProfileMe Mode Programming Guidelines 11shows the counter modes that are used with Aggregate modeThis input counts Mbox replay traps 12 Cmov Decomposed 13 ProfileMe Mode Returned IPR Contents 22Privileged Architecture Library Code ProfileMe Counting Mode Description Cycle counting Inum retire delay cycles 14 ProfileMe Mode Pctrctl Input Select Fields 14shows the counter modes that are used with ProfileMe modeCounter Modes for ProfileMe Mode 24Privileged Architecture Library Code 21264/EV68A Reset State Machine Major Operations Initialization and ConfigurationPower-Up Reset Flow and the ResetL and Dcokh Pins Initialization and Configuration Power-Up Reset Flow and the ResetL and Dcokh Pins Constraints Power Sequencing and Reset State for Signal Pins Signal Pin Reset State Clock Forwarding and System Clock Ratio Configuration Pllvdd Pin Signal Names and Initialization State PLL PLL Ramp Up BiST and Srom Load and the TestStatH Pin Clock Forward Reset and System Interface Initialization Power-Up Flow Signals and Their ConstraintsEV68A Fault Reset Flow Fault Reset FlowEffect on IPRs After Fault Reset Energy Star Certification and Sleep Mode Flow Energy Star Certification and Sleep Mode Flow Effect on IPRs After Transition Through Sleep Mode 10Initialization and Configuration Signals and Constraints for the Sleep Mode Sequence Warm Reset FlowWarm Reset Flow Effect on IPRs After Warm Reset Array Initialization Initialization Mode Processing12Initialization and Configuration Array Initialization Initialization Mode Processing Evictenable BCWRTSTS30 Bcbankenable 14Initialization and Configuration Internal Processor Register Power-Up Reset State10 Internal Processor Registers at Power-Up Reset State External Interface Initialization Internal Processor Register Power-Up Reset State Ieee 1149.1 Test Port Reset Ieee 1149.1 Test Port ResetReset State Machine 16Initialization and Configuration Reset State Machine 11 21264/EV68A Reset State Machine State Descriptions 18Initialization and Configuration Differential Reference Clocks Phase-Lock Loop PLL Functional DescriptionPhase-Lock Loop PLL Functional Description PLL Output Clocks Power-Up/Reset Clocking 20Initialization and Configuration Error Detection and Error Handling 21264/EV68A Error Detection MechanismsError Detection and Error Handling Dcache Tag Parity Error Data Error Correction CodeIcache Data or Tag Parity Error Data Error Correction Code Dcache Data Single-Bit Correctable ECC Error Dcache Data Single-Bit Correctable ECC ErrorLoad Instruction Dcache Store Second Error Dcache Store Second ErrorDcache Duplicate Tag Parity Error Store Instruction Quadword or Smaller Bcache Tag Parity Error Bcache Tag Parity ErrorBcache Data Single-Bit Correctable ECC Error Controlling Bcache Block Parity Calculation Bcache Data Single-Bit Correctable ECC Error Dcache Fill from Bcache Bcache Victim Read Memory/System Port Single-Bit Data Correctable ECC ErrorMemory/System Port Single-Bit Data Correctable ECC Error Icache Fill from Memory Dcache Fill from Memory Bcache Data Single-Bit Correctable ECC Error on a Probe Double-Bit Fill ErrorsBcache Data Single-Bit Correctable ECC Error on a Probe 3summarizes the various error cases and their ramifications Error Case SummaryError Case Summary Section D.36 CRD Cstatprobebcerr Mchk CstatistreammemerrCstatdstreammemerr Mchk CstatistreambcdblPage 1lists the maximum electrical ratings for the 21264/EV68A Electrical CharacteristicsElectrical Data Maximum Electrical Ratings Signal Types DC CharacteristicsDC Characteristics Idcpower Input Differential Amplifier Receiver IDA VDD IdcpowerInput DC Reference Pin Idcref Input Differential Amplifier Clock Receiver Idaclk IOZ Pin Type Open-Drain Driver for Test Pins OodtpPin Type Open-Drain Output Driver OOD Codtp 11 Push-Pull Output Driver OPP 12 Push-Pull Output Clock Driver Oppclk AC Characteristics AC CharacteristicsAC Test Conditions 13 AC Specifications TSU1 TDH2 Dcokh AC Characteristics Page Thermal Management Operating TemperatureOperating Temperature at Heat Sink Center Tc That causes thermal failure Operating Temperature Θca at Various Airflows for 21264/EV68A10-2Thermal Management Heat Sink Specifications Heat Sink Specifications Type 2 Heat Sink 10-4Thermal Management Type 3 Heat Sink Thermal Design Considerations Thermal Design Considerations10-6Thermal Management Dedicated Test Port Pins Testability and DiagnosticsTest Pins Testability and Diagnostics 11-2Testability and Diagnostics SROM/Serial Diagnostic Terminal PortSROM/Serial Diagnostic Terminal Port Srom Load Operation Ieee 1149.1 Port Ieee 1149.1 PortIeee 1149.1 Instructions and Opcodes TestStatH Pin 11-4Testability and DiagnosticsTestStatH Pin TAP Controller State Machine Built-in Self-Test Power-Up Self-Test and InitializationPower-Up Self-Test and Initialization Srom Initialization 11-6Testability and Diagnostics Serial Instruction Cache Load Operation See Appendix B for a listing of the Boundary-Scan Register Icache Bit Fields in an Srom LineReferences Page Table A-1 Instruction Format and Opcode Notation Alpha Instruction SetAlpha Instruction Summary Alpha Instruction Set A-1 Alpha Instruction Summary Opr 11.24 Cmove if = zero Mbr Branch to subroutinePcd Trap to PALcode Opr 11.46 Cmove if ≥ zero 15.0BC Convert quadword to Ffloating 15.0AF Convert Gfloating to quadword17.010 Convert longword to quadword 15.0BE Convert quadword to Gfloating 17.02C Fcmove if zero 17.02F Fcmove if zero17.02E Fcmove if ≤ zero 17.02B Fcmove if ≠ zero Opr 1C.31 Pixel error Opr 13.40 Multiply longword with integer overflow enableOpr 13.60 Multiply quadword with integer overflow enable Mem Load Sfloating Mfc 18.C000 Read process cycle counter 18.F000 Read and set Opr 1C.36 Pack words to bytes Mfc 18.E000 Read and clearMbr 1A.2 Return from subroutine Opr 10.02 Scaled add longword by Reserved Opcodes Reserved OpcodesOpcodes Reserved for Compaq Ieee Floating-Point Instructions Ieee Floating-Point InstructionsOpcodes Reserved for PALcode 02B 06B 08B 00B 04B18B 10B 14B 12B 16B VAX Floating-Point Instructions Independent Floating-Point InstructionsVAX Floating-Point Instructions Opcode Summary Opcode Summary Ieee floating-point instruction opcodes Mem Table A-9explains the symbols used in Table A-8Mem Res Floating-point operate instruction opcodes Ieee Floating-Point Conformance Ieee Floating-Point Conformance14Alpha Instruction Set Table A-11 Exceptional Input and Output Conditions Alpha Instruction Set A-15 16Alpha Instruction Set Cmpteq Cmptun Input Cmptlt Cmptle InputAlpha Instruction Set A-17 Fbeq Fbne Fblt Fble Fbgt Fbge LDS LDT STS STT Cpys Cpysn 21264/EV68A Boundary-Scan Register Boundary-Scan Register Boundary-Scan Register Pllvdd 21264/EV68A Boundary-Scan Register B-3 421264/EV68A Boundary-Scan Register 21264/EV68A Boundary-Scan Register B-5 621264/EV68A Boundary-Scan Register 21264/EV68A Boundary-Scan Register B-7 821264/EV68A Boundary-Scan Register 21264/EV68A Boundary-Scan Register B-9 1021264/EV68A Boundary-Scan Register 21264/EV68A Boundary-Scan Register B-11 1221264/EV68A Boundary-Scan Register Serial Icache Load Predecode Values Serial Icache Load Predecode Values C-1Page PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-1 2PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-3 4PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-5 Initwritemany 6PALcode Restrictions and Guidelines PALcode Restrictions and Guidelines D-7 8PALcode Restrictions and Guidelines Restriction 7 Replay Trap, Interrupt Code Sequence, and STF PALcode Restrictions and Guidelines D-9 Restriction 9 PALmode Istream Address Ranges Restriction 10 Duplicate IPR Mode BitsRestriction 9 PALmode Istream Address Ranges 10PALcode Restrictions and Guidelines Restriction 13 DTB Fill Flow Collision Restriction 11 Ibox IPR Update SynchronizationRestriction 11 Ibox IPR Update Synchronization Restriction 14 Hwret Restriction 21 HWRET/STALL After Hwmtpr ASN0/ASN1 Guideline 20 Ictlsbe Stream Buffer EnableGuideline 16 JSR-BAD VA Guideline 16 JSR-BAD VA Restriction 22 HWRET/STALL After Hwmtpr IS0/IS1 Restriction 22 HWRET/STALL After Hwmtpr IS0/IS1PALcode Restrictions and Guidelines D-13 Restriction 24 HWRET/STALL After Hwmtpr ICFLUSH, Icflushasm Restriction 25 Hwmtpr Itbia After ResetGuideline 26 Conditional Branches in PALcode 14PALcode Restrictions and Guidelines Guideline 29 JSR, JMP, RET, and Jsrcor in PALcode Restriction 30 Hwmtpr and Hwmfpr to the Cbox CSRPALcode Restrictions and Guidelines D-15 Restriction 30 Hwmtpr and Hwmfpr to the Cbox CSR 16PALcode Restrictions and Guidelines Restriction 31 ICTLVA48 Update Restriction 31 ICTLVA48 UpdateRestriction 32 Pctrctl Update PALcode Restrictions and Guidelines D-17 Restriction 36 Updating Ictlsde Guideline 35 Hwintclr UpdateRestriction 33 Hwld Physical/Lock Use Restriction 37 Updating VACTLVA48 Restriction 40 Scrubbing a Single-Bit Error PALcode Restrictions and Guidelines D-19 Restriction 40 Scrubbing a Single-Bit Error 20PALcode Restrictions and Guidelines Restriction 42 Updating VACTL, CCCTL, or CC IPRs Restriction 43 No Trappable Instructions Along withPALcode Restrictions and Guidelines D-21 Restriction 47 Cache Eviction for Single-Bit Cache Errors 22PALcode Restrictions and Guidelines Restriction 47 Cache Eviction for Single-Bit Cache Errors PALcode Restrictions and Guidelines D-23 24PALcode Restrictions and Guidelines 21264/EV68A-to-Bcache Pin Interface Forwarding Clock Pin GroupingsTable E-1 Bcache Forwarding Clock Pin Groupings Data Pin Usage Late-Write Non-Bursting SSRAMsLate-Write Non-Bursting SSRAMs Tag Pin Usage Dual-Data Rate SSRAMs Dual-Data Rate SSRAMsTable E-4 Dual-Data Rate Ssram Data Pin Usage Trstl Table E-5 Dual-Data Rate Ssram Tag Pin Usage421264/EV68A-to-Bcache Pin Interface 21264/EV68A-to-Bcache Pin Interface E-5 Page Glossary BIU BSR Cisc CPU CmosCPI CSR DTB DMADram DTL FEU FepromFET Fpga Gclk IDU ITB IowbIpga Jfet MBZ MAFMBO Mips Nmos MSINaturally Aligned Nvram PLA PALPGA Plcc RAM PqfpProm RAS RTL RiscROM SAM SIP SdramSimm Sipp Uart StramTTL Unaligned VAF UnpredictableUvprom VDF WAR Writeblock Index Numerics Index-2 Index-3 Index-4 ECC Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12