Compaq EV68A specifications TB Fill Flow Example Sequence, 34Internal Architecture

I/O Write Buffer and the WMB Instruction

c.When a probe response has been sent to the system for the marked probe queue entry, the Cbox considers the WMB to be satisfied.

•If Cbox CSR SYSBUS_MB_ENABLE is set, the Cbox performs the following actions:

a.Stalls further MAF and IOWB processing.

b.Sends the MB command to the system port.

c.Waits until the MB command is acknowledged by the system with a SysDc MBDone command, then sends acknowledge and marks the youngest entry in the probe queue.

d.When a probe response has been sent to the system for the marked probe queue entry, the Cbox considers the WMB to be satisfied.

2.12.1.3 TB Fill Flow

Load instructions (HW_LDs) to a virtual page table entry (VPTE) are processed by the 21264/EV68A to avoid litmus test problems associated with the ordering of memory transactions from another processor against loading of a page table entry and the subse- quent virtual-mode load from this processor.

Consider the sequence shown in Table 2–12.The data could be in the Bcache. Pj should fetch datai if it is using PTEi.

Table 2–12 TB Fill Flow Example Sequence 1

Pi	Pj
Write Datai	Load/Store datai
MB	<TB miss>
Write PTEi	Load-PTE
	<write TB>
	Load/Store (restart)

Also consider the related sequence shown in Table 2–13.In this case, the data could be cached in the Bcache; Pj should fetch datai if it is using PTEi.

Table 2–13 TB Fill Flow Example Sequence 2

Pi	Pj
Write Datai	Istream read datai
MB	<TB miss>
Write PTEi	Load-PTE
	<write TB>
	Istream read (restart) - will miss the Icache

The 21264/EV68A processes Dstream loads to the PTE by injecting, in hardware, some memory barrier processing between the PTE transaction and any subsequent load or store instruction. This is accomplished by the following mechanism:

1. The integer queue issues a HW_LD instruction with VPTE.

2–34Internal Architecture 21264/EV68A Hardware Reference Manual