Chapter 1: Introduction to the EIU 31

Figure 7 DMS SuperNode FLIS with an EIU

 

 

F-bus 0

EIU

 

 

 

MS 0

DS512 links

Bus

 

plane 0

 

 

 

 

 

 

EIU

MS 1

 

 

Ethernet

 

Bus

 

 

 

 

 

 

plane1

EIU

 

 

 

 

 

F-bus 1

 

Ethernet interface card (NT9X84)

The EIC is based on commercial Ethernet interface chips. It supports one Ethernet communications link and processes all of the level 1 and part of the level 2 protocols for the Ethernet in hardware.

The card consists of a common message buffer that is accessed by both the processor and the Ethernet interface chip. On the Ethernet side, an independent controller uses memory-based data structures to locate and transmit and receive data from the links. The controller chip is an Advanced Micro Devices AM7990 LANCE device (a LAN controller for Ethernet) with support devices.

The buffer memory is organized as 192 kilowords x 16 bits (384 kbyte) with parity, and is directly accessible by the processor. Both byte and word access is supported. The processor and the Ethernet control chip contend for access to this memory. The architecture of the memory controller ensures that sufficient memory access bandwidth is allocated to the Ethernet controller, so that underrun or overrun conditions do not occur during transmission or reception of a message.

Figure 8 illustrates the memory and buffer architecture.

DMS-100 Family EIU User Guide TELECOM12

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Cabletron Systems DMS-100 manual Ethernet interface card NT9X84, DMS SuperNode Flis with an EIU