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Appendix H: ASU background information 181
Figure 44 LPP architecture
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| 2 MS 0 | 2 MS 1 | 2 MS 0 | 2 MS 1 |
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| LMS 0 |
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| LMS 1 |
Shelf 0 | Rate | DS30 | 2 DS30 | DS30 | Rate | ||
| adapter |
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| adapter |
Shelf 1 |
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| repeater |
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| repeater | |
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| ASU 0 |
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| ASU 11 |
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Shelf 2 |
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| repeater |
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| repeater | |
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| ASU 12 |
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| ASU 23 |
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Shelf 3 |
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| repeater |
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| repeater | |
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| ASU 24 |
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| ASU 35 |
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The LMS represents the first level of the
Each LMS plane consists of a maximum of 13 circuit packs and paddle boards, and occupies