Cabletron Systems DMS-100 manual Platforms, External routers, Link peripheral processor

Models: DMS-100

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180Appendix H: ASU background information

CDPD XLIU terminates various protocols, such as LAPB and MDLP. XLIUs also store accounting information for data services.

CDPD NIU stores and maintains subscriber routing and mobility information on the NIU software. The NIU contains the software that interfaces with the computing module (CM) for maintenance functions. The NIU also gives the XLIU channelized access to the DMS-100 switch network.

External routers

External routers allows the message transfer part (MTP) routing functionality to reside in the dedicated LIU7s instead of in the digital trunk controller 7 (DTC7). This configuration eliminates the necessity for the DTC7s to be informed of routing changes and thus significantly reduces the volume of messaging to the DTC7s.

Platforms

ASUs are supported on the following platforms:

link peripheral processor (LPP)

single-shelf link peripheral processor (SSLPP)

SuperNode SE link interface shelf (SNSE LIS)

Link peripheral processor

LPPs with a maximum of either 24 or 36 ASUs exist. However multi- application deployment is only supported on the 36-ASU version of the LPP. EIUs are not supported on the 24-slot LPP.

The LPP consists of two basic subsystems: the individual ASUs (LIU7s, EIUs, and so on) and the local message switch (LMS). Figure 44 shows a block diagram of the LPP. This figure illustrates the ASU-LMS interconnection through a duplicated frame transport bus (F-bus) and the DS30 interconnections between the independent planes of the LMS and the corresponding planes of the DMS-bus. Each ASU consists of two circuit packs and a single paddle board.

The duplicated F-bus is eight bits wide and runs at a clock rate of 4.096 MHz. Each of the ASUs and services has access to the duplicated F-bus through its ASU F-bus interface. The F-bus terminator and repeater electrically terminates the F-bus and provides a signal repeater function between the ASU shelves within a single LPP. These circuit packs occupy the extreme left and right slot positions in each shelf. Each circuit pack serves one of the duplicated F-bus paths on a single ASU shelf backplane.

297-8991-910 Standard 03.01 August 1999

Page 180
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Cabletron Systems DMS-100 manual Platforms, External routers, Link peripheral processor